Patents by Inventor Chock H. Gan
Chock H. Gan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9070551Abstract: A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to a supply rail and continuous from the left edge to the right edge of the CDC cell; a first polysilicon gate disposed above the p-doped diffusion region and electrically connected to the p-doped diffusion region; an n-doped diffusion region electrically connected to a ground rail and continuous from the left edge to the right edge; a second polysilicon gate disposed above the n-doped diffusion region and electrically connected to the n-doped diffusion region; a left floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the left edge; and a right floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the right edge.Type: GrantFiled: August 23, 2013Date of Patent: June 30, 2015Assignee: Qualcomm IncorporatedInventors: Benjamin John Bowers, James W. Hayward, Charanya Gopal, Gregory Christopher Burda, Robert J. Bucki, Chock H. Gan, Giridhar Nallapati, Matthew D. Youngblood, William R. Flederbach
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Publication number: 20150064864Abstract: A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to a supply rail and continuous from the left edge to the right edge of the CDC cell; a first polysilicon gate disposed above the p-doped diffusion region and electrically connected to the p-doped diffusion region; an n-doped diffusion region electrically connected to a ground rail and continuous from the left edge to the right edge; a second polysilicon gate disposed above the n-doped diffusion region and electrically connected to the n-doped diffusion region; a left floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the left edge; and a right floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the right edge.Type: ApplicationFiled: November 11, 2014Publication date: March 5, 2015Inventors: Benjamin John BOWERS, James W. HAYWARD, Charanya GOPAL, Gregory Christopher BURDA, Robert J. BUCKI, Chock H. GAN, Giridhar NALLAPATI, Matthew D. YOUNGBLOOD, William R. FLEDERBACH
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Publication number: 20140367760Abstract: A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to a supply rail and continuous from the left edge to the right edge of the CDC cell; a first polysilicon gate disposed above the p-doped diffusion region and electrically connected to the p-doped diffusion region; an n-doped diffusion region electrically connected to a ground rail and continuous from the left edge to the right edge; a second polysilicon gate disposed above the n-doped diffusion region and electrically connected to the n-doped diffusion region; a left floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the left edge; and a right floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the right edge.Type: ApplicationFiled: August 23, 2013Publication date: December 18, 2014Applicant: Qualcomm IncorporatedInventors: Benjamin John BOWERS, James W. HAYWARD, Charanya GOPAL, Gregory Christopher BURDA, Robert J. BUCKI, Chock H. GAN, Giridhar NALLAPATI, Matthew D. YOUNGBLOOD, William R. FLEDERBACH
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Patent number: 8782576Abstract: A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to a supply rail and continuous from the left edge to the right edge of the CDC cell; a first polysilicon gate disposed above the p-doped diffusion region and electrically connected to the p-doped diffusion region; an n-doped diffusion region electrically connected to a ground rail and continuous from the left edge to the right edge; a second polysilicon gate disposed above the n-doped diffusion region and electrically connected to the n-doped diffusion region; a left floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the left edge; and a right floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the right edge.Type: GrantFiled: August 26, 2013Date of Patent: July 15, 2014Assignee: QUALCOMM IncorporatedInventors: Benjamin John Bowers, James W. Hayward, Charanya Gopal, Gregory Christopher Burda, Robert J. Bucki, Chock H. Gan, Giridhar Nallapati, Matthew D. Youngblood, William R. Flederbach
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Publication number: 20140181761Abstract: Embodiments of the disclosure include identifying circuit elements for selective inclusion in speed-push processing and related circuit systems, apparatus, and computer-readable media. A method for altering a speed-push mask is provided, including analyzing a circuit design comprising a plurality of cells to which a speed-push mask is applied to identify at least one of the plurality of cells as having performance margin. The speed-push mask is altered such that the at least one of the plurality of cells having performance margin may be fabricated as a non-speed-pushed cell. Additionally, a method for creating a speed-push mask is provided, including analyzing a circuit design comprising a plurality of cells to identify at least one of the plurality of cells below a performance threshold. A speed-push mask is created such that the at least one of the plurality of cells below the performance threshold may be fabricated as a speed-pushed cell.Type: ApplicationFiled: December 21, 2012Publication date: June 26, 2014Applicant: QUALCOMM IncorporatedInventors: Jeffrey H. Fischer, William R. Flederbach, Kyungseok Kim, Robert J. Bucki, Chock H. Gan, William J. Goodall, III
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Patent number: 8610176Abstract: An apparatus fabricated using a standard cell architecture including devices having different voltage thresholds may include a first set of polylines associated with a first channel length, where each polyline within the first set of polylines is separated by a substantially constant pitch. The apparatus may further include a second set of polylines associated with a second channel length and aligned with the first set of polylines, where each polyline within the second set of polylines is laterally separated by the substantially constant pitch. The apparatus may further include a first active region below the first set of polylines, and a second active region below the second set of polylines, where the first active region and the second active region are separated by a distance of less than 170 nm.Type: GrantFiled: January 11, 2011Date of Patent: December 17, 2013Assignee: QUALCOMM IncorporatedInventors: Prayag B. Patel, Pratyush Kamal, Foua Vang, Chock H. Gan, Pr Chidambaram, Chethan Swamynathan
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Patent number: 8558320Abstract: An integrated circuit device comprising a first elongate structure and a second elongate structure arranged parallel to each other and defining a space therebetween. The integrated circuit device also includes conductive structures distributed in the space between the first and second elongate structures. At least a first one of the conductive structures is placed closer to the first elongate structure than to the second elongate structure. At least a second one of the conductive structures is placed closer to the second elongate structure than to the first elongate structure.Type: GrantFiled: December 15, 2009Date of Patent: October 15, 2013Assignee: QUALCOMM IncorporatedInventors: Haining Yang, Chock H. Gan, Zhongze Wang, Beom-Mo Han
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Publication number: 20120180016Abstract: An apparatus fabricated using a standard cell architecture including devices having different voltage thresholds may include a first set of polylines associated with a first channel length, where each polyline within the first set of polylines is separated by a substantially constant pitch. The apparatus may further include a second set of polylines associated with a second channel length and aligned with the first set of polylines, where each polyline within the second set of polylines is laterally separated by the substantially constant pitch. The apparatus may further include a first active region below the first set of polylines, and a second active region below the second set of polylines, where the first active region and the second active region are separated by a distance of less than 170 nm.Type: ApplicationFiled: January 11, 2011Publication date: July 12, 2012Applicant: QUALCOMM INCORPORATEDInventors: PR Chidambaram, Prayag B. Patel, Foua Vang, Pratyush Kamal, Chock H Gan, Chethan Swamynathan
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Publication number: 20110140288Abstract: An integrated circuit device comprising a first elongate structure and a second elongate structure arranged parallel to each other and defining a space therebetween. The integrated circuit device also includes conductive structures distributed in the space between the first and second elongate structures. At least a first one of the conductive structures is placed closer to the first elongate structure than to the second elongate structure. At least a second one of the conductive structures is placed closer to the second elongate structure than to the first elongate structure.Type: ApplicationFiled: December 15, 2009Publication date: June 16, 2011Applicant: QUALCOMM INCORPORATEDInventors: Haining Yang, Chock H. Gan, Zhongze Wang, Beom-Mo Han
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Patent number: 6027982Abstract: A method to form shallow trench isolation structures with improved isolation fill and surface planarity is described. A pad oxide layer is provided over the surface of a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. A thin oxide layer is deposited overlying the silicon nitride layer. An isolation trench is etched through the thin oxide layer, the nitride layer, and the pad oxide layer and into the substrate. The silicon nitride layer exposed within the trench is etched to form a lateral undercut leaving a projection of the thin oxide layer and exposing a portion of the underlying pad oxide layer. The thin oxide layer and the exposed portion of the pad oxide layer are etched away thereby exposing portions of the surface of the substrate. A liner oxide is grown on the exposed portions of the semiconductor substrate within the isolation trench and on the surface of the substrate.Type: GrantFiled: February 5, 1999Date of Patent: February 22, 2000Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Igor V. Peidous, Vladislav Y. Vassiliev, Chock H. Gan, Guang Ping Hua
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Patent number: 5856225Abstract: A method of fabricating a MOSFET device, in which a source and drain region has been formed, prior to the formation of an ion implanted channel region, has been developed. The early creation of source and drain region allows a high temperature anneal to be performed, removing damage resulting from the source and drain ion implantation procedures, however without redistribution of channel dopants. The method features creating an opening in an insulator layer, after the source and drain formation, and then forming the channel region in the semiconductor substrate, directly underlying the opening in the insulator layer. A polysilicon gate structure is next formed in the opening, resulting in self-alignment to the underlying channel region.Type: GrantFiled: November 24, 1997Date of Patent: January 5, 1999Assignee: Chartered Semiconductor Manufacturing LtdInventors: Teck Koon Lee, Lap Chan, Chock H. Gan, Po-Ching Liu