Abstract: A method includes receiving a first circuit design, deriving circuit design revisions based on the first circuit design, receiving revision information for each of the circuit design revisions that is output as a result of compilation of the circuit design revisions, extracting location information, timing information, or both for resources from the revision information, for each of the circuit design revisions, mapping the resources into a chip view based on the location information, the timing information, or both. The chip view includes a virtual visualization of an actual physical chip and the resources are mapped to their actual locations on the virtual visualization as they would be implemented on the actual physical chip. The method also includes generating the chip view of the circuit design revisions that displays a report specific to one or more properties of the circuit design revisions.

Abstract: A method of displaying a schematic diagram of an integrated circuit design is disclosed. The integrated circuit design includes a plurality of logic blocks and the schematic diagram may include a plurality of connections between respective pairs or groups of the logic blocks. The method includes identifying a plurality of interconnect lines that is adapted to schematically illustrate the plurality of connections. Selected interconnect lines out of the plurality of interconnect lines is identified. Portions of the selected interconnect lines may be channeled through a global connection line on the schematic diagram. The global connection line may be a graphical line that spans from one edge of the schematic diagram to another.

Abstract: The interactive grouping tool offers the flexibility to simplify the schematic diagram of an integrated circuit (IC) design by grouping circuit elements that are not specified to be of interest into entities of any size. Circuit elements of various types and functionalities, including ports and pins, can be combined together into the same entity without modifying the underlying design logic and connectivity. By grouping and hiding the unnecessary details, the tool reduces clutter in a schematic diagram and greatly eases the process of traversing, debugging, and analyzing the schematic diagram. Users can choose to dynamically group the circuit elements on the schematic diagram without going through any compilation or synthesis process. Users can also choose to revert any of the entities back to the original schematic diagram with the ungrouping operation. For specific or batch manipulation of the schematic diagram, the tool provides a scripting interface for users to enter commands.

Abstract: The number of nodes in an RTL schematic is reduced in a process of cloud grouping, a process whereby nodes that are not specified to be of interest will be grouped into a cloud to the extent possible. This results in a much simplified schematic as the remaining nodes within the schematic will be those nodes that the users desire to see. Analysis of all nodes including those designated as cut nodes is performed to determine what circuitry can or cannot be simplified. The user will also have the option to revert to the original schematic if viewing more than the cut nodes is desirable.

Abstract: The number of nodes in an RTL schematic is reduced in a process of cloud grouping, a process whereby nodes that are not specified to be of interest will be grouped into a cloud to the extent possible. This results in a much simplified schematic as the remaining nodes within the schematic will be those nodes that the users desire to see. Analysis of all nodes including those designated as cut nodes is performed to determine what circuitry can or cannot be simplified. The user will also have the option to revert to the original schematic if viewing more than the cut nodes is desirable.

Abstract: The interactive grouping tool offers the flexibility to simplify the schematic diagram of an integrated circuit (IC) design by grouping circuit elements that are not specified to be of interest into entities of any size. Circuit elements of various types and functionalities, including ports and pins, can be combined together into the same entity without modifying the underlying design logic and connectivity. By grouping and hiding the unnecessary details, the tool reduces clutter in a schematic diagram and greatly eases the process of traversing, debugging, and analyzing the schematic diagram. Users can choose to dynamically group the circuit elements on the schematic diagram without going through any compilation or synthesis process. Users can also choose to revert any of the entities back to the original schematic diagram with the ungrouping operation. For specific or batch manipulation of the schematic diagram, the tool provides a scripting interface for users to enter commands.