Abstract: A microelectronic unit can include a lead frame and a device chip. The lead frame can have a plurality of monolithic lead fingers extending in a plane of the lead frame. Each lead finger can have a fan-out portion and a chip connection portion extending in the lead frame plane. The fan-out portions can have first and second opposed surfaces and a first thickness in a first direction between the opposed surfaces. The chip connection portions can have a second thickness smaller than the first thickness. The chip connection portions can define a recess below the first surface. The device chip can have a plurality of at least one of passive devices or active devices. The device chip can have contacts thereon facing the chip connection portions and electrically coupled thereto. At least a portion of a thickness of the device chip can extend within the recess.

Abstract: A microelectronic unit can include a lead frame and a device chip. The lead frame can have a plurality of monolithic lead fingers extending in a plane of the lead frame. Each lead finger can have a fan-out portion and a chip connection portion extending in the lead frame plane. The fan-out portions can have first and second opposed surfaces and a first thickness in a first direction between the opposed surfaces. The chip connection portions can have a second thickness smaller than the first thickness. The chip connection portions can define a recess below the first surface. The device chip can have a plurality of at least one of passive devices or active devices. The device chip can have contacts thereon facing the chip connection portions and electrically coupled thereto. At least a portion of a thickness of the device chip can extend within the recess.

Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the ground plane used to ground the low speed circuitry of the package.

Abstract: A routing pattern for high speed signals for a package substrate. Electrically conductive bond fingers are disposed on a first surface of the package substrate. The first surface is adapted to receive an integrated circuit in an attachment zone, and the bond fingers are disposed in at least two substantially concentric rings around the attachment zone. The bond fingers of the innermost ring of bond fingers are all routed to electrically conductive first traces disposed on a first layer of the package substrate. The bond fingers other that those on the innermost ring of bond fingers are all routed to electrically conductive second traces disposed on a separate second layer of the package substrate. The package substrate has electrically conductive traces on only the first layer and the second layer. Electrically conductive contacts are disposed on a substantially opposing second surface.

Abstract: A bond pad structure which improves the reliability of the gold bonds, and thus, of the device. The bond pad structure allows for small gold bonds, which increases the density of the device. One design provides that the aluminum pad is connected to the copper IO strap at one end only. As such, expansion of the aluminum pad is not constrained. Another design provides that a segmented or un-segmented square copper ring is provided under the aluminum pad. There is effectively no copper provided under the aluminum pad in the area under the gold ball band. This reduces the restriction of the expansion of the aluminum pad. Yet another design provides for a reduced copper pad size under the aluminum pad, preferably just large enough for electrical connection.

Abstract: A package for reducing signal cross talk between wire bonds of semiconductor packages. The package includes a semiconductor die having a plurality of bond pads formed thereon. The bond pads arranged in a first subset of bond pads and a second subset of bond pads. The package also includes a substrate having a plurality of contact points, the plurality of contact points are arranged in a first subset of contact points and a second subset of contact points. To reduce signal cross talk, the wire bonds are arranged such that a first subset of wire bonds are electrically coupled between the first subset of bond pads and the first subset of the contact points. The first subset of wire bonds have ball bonds formed on the first subset of bond pads and stitch bonds formed on the first subset of contact points respectively. A second subset of wire bonds are electrically coupled between the second subset of bond pads and the second subset of the contact points.

Abstract: A method wherein a substrate with plating tails is formed or otherwise provided, such as by performing a conventional electroplating process. Subsequently, a laser is used to remove some or all of the plating tails or a portion of some or all of the plating tails. If portions or remnants of the plating tails are to remain, the plating tails can be connected to ground. By connecting the remnants of the plating tails to ground, an electrical performance enhancement can be realized. Specifically, additional shielding in the package can be provided. Furthermore, the plating tails can be specifically designed to enhance the amount of shielding they provide.