Abstract: A storage device includes a memory including a plurality of regions arranged along a first axis and a second axis orthogonal to each other, each of the plurality of regions belonging to one of first groups and one of second groups; and a controller configured to, when a programmed and weak region exists, put into a scan list on the basis of a weak list, a programmed and weak sub-region included in the programmed and weak region among the plurality of regions, put into the scan list, a first programmed and adjacent sub-region in a first programmed and adjacent region selected according to a second axis expansion order among the plurality of regions, and put into the scan list, a second programmed and adjacent sub-region in a second programmed and adjacent region selected according to a first axis expansion order among the plurality of regions.

Abstract: A memory system includes a memory device and a controller. The memory device includes a plurality of memory blocks for storing or outputting plural data entries and a first parity entry associated with the plural data entries. The controller a second parity entry based on a part of the plural data entries, an updated data entry which renews the part of the plural data entries, and the first parity entry, in response to an update event regarding the part of the plural data entries, allocate, for storing the second parity entry, a first memory block having least program-erase cycles among the plurality of memory blocks, allocate, for storing the updated data entry, a second memory block storing the first parity entry, and control the memory device to program the updated data entry and the second parity entry in the first memory block and the second memory block.

Abstract: A memory system includes a memory device including a plurality of memory blocks and a controller suitable for controlling the memory device to store a read retry table that includes a plurality of read bias sets respectively corresponding to a plurality of indexes; controlling the memory device to perform a read retry operation with the read bias sets according to an ascending order of the indexes; updating, when a read operation is successfully performed during the read retry operation, the read retry table by including the read levels of the successful read operation into a read bias set of a highest priority index within the read retry table; and controlling the memory device to perform a subsequent read retry operation based on the updated read retry table.

Abstract: A storage device includes a memory including a plurality of regions arranged along a first axis and a second axis orthogonal to each other, each of the plurality of regions belonging to one of first groups and one of second groups; and a controller configured to, when a programmed and weak region exists, put into a scan list on the basis of a weak list, a programmed and weak sub-region included in the programmed and weak region among the plurality of regions, put into the scan list, a first programmed and adjacent sub-region in a first programmed and adjacent region selected according to a second axis expansion order among the plurality of regions, and put into the scan list, a second programmed and adjacent sub-region in a second programmed and adjacent region selected according to a first axis expansion order among the plurality of regions.

Abstract: A random seed generating circuit of a memory system includes a first address generating circuit, a second address generating circuit, a table circuit and a seed generating circuit. The first address generating circuit generates an initial address based on target page information. The second address generating circuit generates a plurality of table addresses based on the target page information and a plurality of partial addresses, which are divided from the initial address. The table circuit outputs, from a plurality of tables, a plurality of table values respectively corresponding to the plurality of table addresses. The seed generating circuit generates a random seed based on the plurality of table values.

Abstract: A parity check matrix managing technology generating and modifying parity check matrix for encoding and decoding data to be processed in a communication system, memory system, and the like is disclosed. A parity check matrix managing apparatus may include an input device configured to receive a parity check matrix as a modification target; a matrix modifier configured to modify the parity check matrix by performing at least one of a cyclic shift on unit components of at least one row or column in the parity check matrix and a location change between at least two rows or columns in the parity check matrix to generate a modified parity check matrix; and a controller configured to control the matrix modifier to compare a matrix size of the modified parity check matrix with a set matrix size, so that the matrix size is less than or equal to the set matrix size.

Abstract: An H matrix generating circuit for generating an H matrix of a QC-LDPC code may include: a conversion value calculation unit calculating conversion values corresponding to column sections of an original H matrix including a plurality of circulant matrices; and a shift unit generating an advanced H matrix by circularly shifting circulant matrices positioned in column sections of the original H matrix by amounts of the conversion values, respectively.

Abstract: A memory system includes a memory device including a plurality of memory blocks and a controller suitable for controlling the memory device to store a read retry table that includes a plurality of read bias sets respectively corresponding to a plurality of indexes; controlling the memory device to perform a read retry operation with the read bias sets according to an ascending order of the indexes; updating, when a read operation is successfully performed during the read retry operation, the read retry table by including the read levels of the successful read operation into a read bias set of a highest priority index within the read retry table; and controlling the memory device to perform a subsequent read retry operation based on the updated read retry table.

Abstract: A parity check matrix managing technology generating and modifying parity check matrix for encoding and decoding data to be processed in a communication system, memory system, and the like is disclosed. A parity check matrix managing apparatus may include an input device configured to receive a parity check matrix as a modification target; a matrix modifier configured to modify the parity check matrix by performing at least one of a cyclic shift on unit components of at least one row or column in the parity check matrix and a location change between at least two rows or columns in the parity check matrix to generate a modified parity check matrix; and a controller configured to control the matrix modifier to compare a matrix size of the modified parity check matrix with a set matrix size, so that the matrix size is less than or equal to the set matrix size.

Abstract: A semiconductor device includes a controller and a memory device. The controller includes a processor configured to process a request from an external apparatus, an interface configured to receive the request and data from the external apparatus and an ECC encoder configured to generate, in response to the request, a data block matrix including a plurality of data block groups and a plurality of parity blocks that are generated based on the received data, and to generate encoded data by adding parity information to the data block matrix, the encoded data being transmitted to the memory device.

Abstract: A parity check matrix generator for generating a parity check matrix including non-binary cyclic permutation matrices may include: a first memory configured to store a first weight as location information on a non-binary cyclic permutation matrix within the parity check matrix; a second memory configured to store a second weight as cyclic strength of matrix elements of the non-binary cyclic permutation matrix; a third memory configured to store a third weight used to determine a size of a non-binary matrix element among the matrix elements of the non-binary cyclic permutation matrix; and a matrix generator configured to generate the non-binary cyclic permutation matrix by applying a non-binary value to matrix elements of 1's among matrix elements of a binary cyclic permutation matrix having a size corresponding to the non-binary cyclic permutation matrix and reflecting one or more of the first to third weights into the non-binary value.

Abstract: A parity check matrix generator for generating a parity check matrix including non-binary cyclic permutation matrices may include: a first memory configured to store a first weight as location information on a non-binary cyclic permutation matrix within the parity check matrix; a second memory configured to store a second weight as cyclic strength of matrix elements of the non-binary cyclic permutation matrix; a third memory configured to store a third weight used to determine a size of a non-binary matrix element among the matrix elements of the non-binary cyclic permutation matrix; and a matrix generator configured to generate the non-binary cyclic permutation matrix by applying a non-binary value to matrix elements of 1's among matrix elements of a binary cyclic permutation matrix having a size corresponding to the non-binary cyclic permutation matrix and reflecting one or more of the first to third weights into the non-binary value.

Abstract: A memory system may include: a memory device including a plurality of pages for storing data and a plurality of memory blocks including the pages; and a controller configured to read data, which corresponds to a read command received from a host, from the pages, perform bit flipping with respect to a plurality of constituent codes for the read data, and perform an error correction operation, the bit flipping is updated corresponding to a number of error correction bits in the constituent codes.

Abstract: A semiconductor device includes a controller and a memory device. The controller includes a processor configured to process a request from an external apparatus, an interface configured to receive the request and data from the external apparatus and an ECC encoder configured to generate, in response to the request, a data block matrix including a plurality of data block groups and a plurality of parity blocks that are generated based on the received data, and to generate encoded data by adding parity information to the data block matrix, the encoded data being transmitted to the memory device.

Abstract: An H matrix generating circuit for generating an H matrix of a QC-LDPC code may include: a conversion value calculation unit calculating conversion values corresponding to column sections of an original H matrix including a plurality of circulant matrices; and a shift unit generating an advanced H matrix by circularly shifting circulant matrices positioned in column sections of the original H matrix by amounts of the conversion values, respectively.

Abstract: A memory system may include: a memory device including a plurality of pages for storing data and a plurality of memory blocks including the pages; and a controller configured to read data, which corresponds to a read command received from a host, from the pages, perform bit flipping with respect to a plurality of constituent codes for the read data, and perform an error correction operation, the bit flipping is updated corresponding to a number of error correction bits in the constituent codes.

Abstract: A method for operating a data storage device includes reading out a data chunk from a nonvolatile memory device; arranging first codes and second codes of the read-out data chunk in the form of a matrix; and determining the total number of corrected error bits for the data chunk by decoding the respective first codes and the respective second codes, and summing the numbers of corrected error bits of the respective decoded first codes and the respective decoded second codes.

Abstract: A test system may include a memory device suitable for reading a stored data chunk; and a test device suitable for calculating a cumulative failure probability that the data chunk will contain a s predetermined number of error bits or less and decoding for the data chunk will fail.

Abstract: A data storage device includes a nonvolatile memory apparatus including a page including a plurality of chunk areas respectively corresponding to a plurality of data chunks; and a controller including a memory, and suitable for generating parity data by independently encoding one of the plural data chunk, storing the data chunk in one of the plural chunk areas of the page and storing the parity data in the memory as intermediate parity data.

Abstract: A data storage device includes a nonvolatile memory apparatus including a target region; and a controller suitable for performing a read voltage adjustment operation including setting a plurality of test read voltages based on a reference read voltage and an offset value, reading a plurality of codewords from the target region by using the plurality of test read voltages, respectively, calculating a plurality of parity check sums respectively corresponding to the plurality of codewords, and selecting a final read voltage based on the plurality of parity check sums.