Abstract: A wafer including at least a first die and at least a second die, wherein the first die and the second die are separated from each other by an area located between the first die and the second die, is provided. The wafer further includes an alignment mark group used for aligning the wafer to a tool used for patterning the wafer. The alignment mark group is located entirely within the area between the first die and the second die and the alignment mark group includes a plurality of alignment lines, and wherein each line of the plurality of alignment lines is formed using a plurality of segments separated from each other by a plurality of gaps filled with an insulating material.

Abstract: A method of making a semiconductor device is achieved in and over a semiconductor layer. A trench is formed adjacent to a first active area. The trench is filled with insulating material. A masking feature is formed over a center portion of the trench to expose a first side of the trench between a first side of the masking feature and the first active area. A step of etching into the first side of the trench leaves a first recess in the trench. A first epitaxial region is grown in the first recess to extend the first active area to include the first recess and thereby form an extended first active region.

Abstract: A method of making a semiconductor device is achieved in and over a semiconductor layer. A trench is formed adjacent to a first active area. The trench is filled with insulating material. A masking feature is formed over a center portion of the trench to expose a first side of the trench between a first side of the masking feature and the first active area. A step of etching into the first side of the trench leaves a first recess in the trench. A first epitaxial region is grown in the first recess to extend the first active area to include the first recess and thereby form an extended first active region.

Abstract: A wafer including at least a first die and at least a second die, wherein the first die and the second die are separated from each other by an area located between the first die and the second die, is provided. The wafer further includes an alignment mark group used for aligning the wafer to a tool used for patterning the wafer. The alignment mark group is located entirely within the area between the first die and the second die and the alignment mark group includes a plurality of alignment lines, and wherein each line of the plurality of alignment lines is formed using a plurality of segments separated from each other by a plurality of gaps filled with an insulating material.

Abstract: A method of making a semiconductor device is achieved in and over a semiconductor layer. A trench is formed adjacent to a first active area. The trench is filled with insulating material. A masking feature is formed over a center portion of the trench to expose a first side of the trench between a first side of the masking feature and the first active area. A step of etching into the first side of the trench leaves a first recess in the trench. A first epitaxial region is grown in the first recess to extend the first active area to include the first recess and thereby form an extended first active region.

Abstract: A method for protecting at least one high-topography region on a substrate having both the at least one high-topography region and the at least one low-topography region is provided. The method comprises patterning a thick photo-resist layer having a first thickness, such that the thick photo-resist layer is formed on at least a portion of only the at least one high-topography region, wherein the high-topography region comprises a plurality of semiconductor devices of a first type. The method further comprises patterning a thin photo-resist layer having a second thickness, wherein the first thickness is greater than the second thickness, such that the patterned thin photo-resist layer is formed on at least a portion of only the at least one low-topography region. The method further comprises forming a plurality of semiconductor devices of a second type in the at least the portion of the low-topography region.

Abstract: A semiconductor fabrication process includes forming a gate stack overlying semiconductor substrate. Source/drain regions are formed in the substrate laterally aligned to the gate stack. A hard mask is formed overlying a gate electrode of the gate stack. A first silicide is then formed selectively over the source/drain regions. After removing the hard mask, a second silicide is selectively formed on the gate electrode. The first silicide and the second silicide are different. Forming the gate stack may include forming a gate dielectric on the semiconductor substrate and a polysilicon gate electrode on the gate dielectric. The gate electrode may have a line width of less than 40 nm. Forming the second silicide may include forming nickel silicide in upper portions of the gate electrode.

Abstract: A semiconductor fabrication process includes forming a gate stack overlying semiconductor substrate. Source/drain regions are formed in the substrate laterally aligned to the gate stack. A hard mask is formed overlying a gate electrode of the gate stack. A first silicide is then formed selectively over the source/drain regions. After removing the hard mask, a second silicide is selectively formed on the gate electrode. The first silicide and the second silicide are different. Forming the gate stack may include forming a gate dielectric on the semiconductor substrate and a polysilicon gate electrode on the gate dielectric. The gate electrode may have a line width of less than 40 nm. Forming the second silicide may include forming nickel silicide in upper portions of the gate electrode.

Abstract: A patterning method allows for separate transfer of a complementary reticle set. In one embodiment, for example, the method includes etching a phase shift mask (PSM), then etching a cut mask for a cPSM mask. Moreover, a decoupled complementary mask patterning transfer method includes two separate and decoupled mask patterning steps which form combined patterns through the use of partial image transfers into an intermediate hard mask prior to final wafer patterning. The intermediate and final hard mask materials are chosen to prevent image transfer into an underlying substrate or wafer prior to the final etch process.

Abstract: A patterning method allows for separate transfer of a complementary reticle set. In one embodiment, for example, the method includes etching a phase shift mask (PSM), then etching a cut mask for a cPSM mask. Moreover, a decoupled complementary mask patterning transfer method includes two separate and decoupled mask patterning steps which form combined patterns through the use of partial image transfers into an intermediate hard mask prior to final wafer patterning. The intermediate and final hard mask materials are chosen to prevent image transfer into an underlying substrate or wafer prior to the final etch process.

Abstract: A resist layer (34) on a semiconductor wafer (20) is patterned by using a scanning exposure system (50) which provides light, containing pattern information which is intended to be transferred to the wafer. The lithographic system is a step and scan system in which a reticle (16) passes between a light source and a lens system(18). The wafer with the resist layer is passed through a focal plane of the patterned light at a tilt angle (&thgr;). The user selects a desirable range for the depth of the resist to be exposed at the focus of the patterned light. The tilt angle is calculated by taking the arc tangent of the desirable range divided by a width of a slit region (52) of the projected light. The depth of focus increases over standard step and scan techniques.

Abstract: A resist layer (34) on a semiconductor wafer (20) is patterned by using a scanning exposure system (50) which provides light, containing pattern information which is intended to be transferred to the wafer. The lithographic system is a step and scan system in which a reticle (16) passes between a light source and a lens system(18). The wafer with the resist layer is passed through a focal plane of the patterned light at a tilt angle (&thgr;). The user selects a desirable range for the depth of the resist to be exposed at the focus of the patterned light. The tilt angle is calculated by taking the arc tangent of the desirable range divided by a width of a slit region (52) of the projected light. The depth of focus increases over standard step and scan techniques.

Abstract: An improved method of integrated circuit fabrication is described with a photolithographic step involving pattern decomposition. A desired final pattern is decomposed into two or more component patterns for photoresist imaging, leading to improvements in image fidelity.

Abstract: A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. An anti-reflective coating helps protect against reflective gate notching. A variety of silicided and non-silicided) structures may be formed.

Abstract: A process for fabricating a semiconductor device includes the formation of a lithographic reticle (20) having a lithographic pattern (18) overlying a reticle substrate (10). In one embodiment, a reticle inspection database incorporates altered resolution assisting features (30,32) to inspect the lithographic pattern (18). The dimensional difference between the reticle inspection database and the lithographic reticle is substantially equal to the process bias realized during reticle fabrication. Inspection of the lithographic reticle (20) using a reticle inspection database containing altered resolution assisting features reduces the false detection of defects and provides increased sensitivity in the reticle inspection process.

Abstract: In the manufacture of integrated-circuit devices, patterned features are made on a substrate by etching a deposited layer. The pattern comprises features which are closely spaced, as well as others which are more isolated. Etching is in approximate conformance with a lithographically defined resist pattern which in turn is in approximate conformance with a desired pattern. A processing parameter such as, e.g., resist layer thickness is chosen such that an etched pattern is obtained which approximates a desired pattern more closely than a lithographically defined resist pattern.

Abstract: Transducer structures for use in volume flow measurements which generate a first uniform beam and a second focused beam within the uniform beam. The transducer may include concentric elements, a linear array, or combinations thereof. In a two element concentric array, a central disc generates a uniform beam and a peripheral annular element having a lens thereon defines a second focused beam within the first beam. In a linear array a plurality of juxtaposed linear elements define a scan surface and a segmented element within the linear element array defines a focused reference sample volume within the scanned surface. A concentric array having a plurality of annular elements is driven with amplitude weighting of each element in accordance with a Fourier-Bessel approximation to the desired beam pattern thereby electronically achieving ultrasonic beam width control.

Abstract: Transducer structures for use in volume flow measurements which generate a first uniform beam and a second focused beam within the uniform beam. The transducer may include concentric elements, a linear array, or combinations thereof. In a two element concentric array, a central disc generates a uniform beam and a peripheral annular element having a lens thereon defines a second focused beam within the first beam. In a linear array, a plurality of juxtaposed linear elements define a scan surface, and a segmented element within the linear element array defines a focused reference sample volume within the scanned surface. A concentric array having a plurality of annular elements is driven with amplitude weighting of each element, in accordance with a Fourier-Bessel approximation to the desired beam pattern, thereby electronically achieving ultrasonic beam width control.