Abstract: Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an integrated circuit chip comprising an exposed backside surface defining a plane, a plurality of wire bonds that are conductively coupled to the integrated circuit chip, each of the plurality of wire bonds being conductively coupled to a conductive exposed portion, a portion of the conductive exposed portion being positioned in the plane defined by the backside surface, and an encapsulant material positioned adjacent the integrated circuit chip and the plurality of wire bonds.

Abstract: A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A first of the conductive planes includes two sets of bond fingers, conductive traces that extend from a first set of the bond fingers, and two sets of redistributed bond pads, including a first set to which the conductive traces lead. The second conductive plane includes conductive traces that extend from locations that are opposite from the second set of bond fingers toward locations that are opposite from the locations of the second set of redistributed bond pads. Conductive vias are formed through the second set of bond fingers to the conductive traces of the second conductive plane. In addition, conductive vias are also formed to electrically connect the conductive vias of the second conductive plane to their corresponding redistributed bond pads in the first conductive plane.

Abstract: A device is disclosed which includes an interposer, at least one capacitor formed at least partially within an opening formed in the interposer and an integrated circuit that is operatively coupled to the interposer. A method is disclosed which includes obtaining an interposer having at least one capacitor formed at least partially within an opening in the interposer and operatively coupling an integrated circuit to the interposer. A method is also disclosed which includes obtaining an interposer comprising a dielectric material, forming an opening in the interposer and forming a capacitor that is positioned at least partially within the opening.

Abstract: A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A first of the conductive planes includes two sets of bond fingers, conductive traces that extend from a first set of the bond fingers, and two sets of redistributed bond pads, including a first set to which the conductive traces lead. The second conductive plane includes conductive traces that extend from locations that are opposite from the second set of bond fingers toward locations that are opposite from the locations of the second set of redistributed bond pads. Conductive vias are formed through the second set of bond fingers to the conductive traces of the second conductive plane. In addition, conductive vias are also formed to electrically connect the conductive vias of the second conductive plane to their corresponding redistributed bond pads in the first conductive plane.

Abstract: A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A first of the conductive planes includes two sets of bond fingers, conductive traces that extend from a first set of the bond fingers, and two sets of redistributed bond pads, including a first set to which the conductive traces lead. The second conductive plane includes conductive traces that extend from locations that are opposite from the second set of bond fingers toward locations that are opposite from the locations of the second set of redistributed bond pads. Conductive vias are formed through the second set of bond fingers to the conductive traces of the second conductive plane. In addition, conductive vias are also formed to electrically connect the conductive vias of the second conductive plane to their corresponding redistributed bond pads in the first conductive plane.

Abstract: A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A first of the conductive planes includes two sets of bond fingers, conductive traces that extend from a first set of the bond fingers, and two sets of redistributed bond pads, including a first set to which the conductive traces lead. The second conductive plane includes conductive traces that extend from locations that are opposite from the second set of bond fingers toward locations that are opposite from the locations of the second set of redistributed bond pads. Conductive vias are formed through the second set of bond fingers to the conductive traces of the second conductive plane. In addition, conductive vias are also formed to electrically connect the conductive vias of the second conductive plane to their corresponding redistributed bond pads in the first conductive plane.

Abstract: A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A first of the conductive planes includes two sets of bond fingers, conductive traces that extend from a first set of the bond fingers, and two sets of redistributed bond pads, including a first set to which the conductive traces lead. The second conductive plane includes conductive traces that extend from locations that are opposite from the second set of bond fingers toward locations that are opposite from the locations of the second set of redistributed bond pads. Conductive vias are formed through the second set of bond fingers to the conductive traces of the second conductive plane. In addition, conductive vias are also formed to electrically connect the conductive vias of the second conductive plane to their corresponding redistributed bond pads in the first conductive plane.

Abstract: An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least a second semiconductor device at least partially over the first semiconductor device. An outer peripheral portion of the second semiconductor device overhangs both the first semiconductor device and the substrate. Discrete conductive elements are placed between the outer peripheral portion of the second semiconductor device and a second surface of the substrate. Intermediate portions of the discrete conductive elements pass outside of a side surface of the substrate. Assemblies and packaged semiconductor devices that are formed in accordance with the method are also disclosed.

Abstract: A semiconductor device package includes a carrier, one or more semiconductor devices on the carrier, and a redistribution element above the uppermost of the one or more semiconductor devices. The redistribution element includes an array of contact pads that communicate with each semiconductor device of the package. The package may also include an encapsulant through which the contact pads of the redistribution element are at least electrically exposed. Methods for assembling and packaging semiconductor devices, as well as methods for assembling multiple packages, including methods for replacing the functionality of one or more defective semiconductor devices of a package according to embodiments of the present invention, are also disclosed.

Abstract: A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A first of the conductive planes includes two sets of bond fingers, conductive traces that extend from a first set of the bond fingers, and two sets of redistributed bond pads, including a first set to which the conductive traces lead. The second conductive plane includes conductive traces that extend from locations that are opposite from the second set of bond fingers toward locations that are opposite from the locations of the second set of redistributed bond pads. Conductive vias are formed through the second set of bond fingers to the conductive traces of the second conductive plane. In addition, conductive vias are also formed to electrically connect the conductive vias of the second conductive plane to their corresponding redistributed bond pads in the first conductive plane.

Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.

Abstract: An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least a second semiconductor device at least partially over the first semiconductor device. An outer peripheral portion of the second semiconductor device overhangs both the first semiconductor device and the substrate. Discrete conductive elements are placed between the outer peripheral portion of the second semiconductor device and a second surface of the substrate. Intermediate portions of the discrete conductive elements pass outside of a side surface of the substrate. Assemblies and packaged semiconductor devices that are formed in accordance with the method are also disclosed.

Abstract: A device is disclosed which includes a flexible material including at least one conductive wiring trace, a first die including at least an integrated circuit, the first die being positioned above a portion of the flexible material, and an encapsulant material that covers the first die and at least a portion of the flexible material. A method is disclosed which includes positioning a first die above a portion of a flexible material, the first die including an integrated circuit and the flexible material including at least one conductive wiring trace, and forming an encapsulant material that covers the first die and at least a portion of the flexible material, wherein at least a portion of the flexible material extends beyond the encapsulant material.

Abstract: An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least a second semiconductor device at least partially over the first semiconductor device. An outer peripheral portion of the second semiconductor device overhangs both the first semiconductor device and the substrate. Discrete conductive elements are placed between the outer peripheral portion of the second semiconductor device and a second surface of the substrate. Intermediate portions of the discrete conductive elements pass outside of a side surface of the substrate. Assemblies and packaged semiconductor devices that are formed in accordance with the method are also disclosed.

Abstract: A device is disclosed which includes a flexible material including at least one conductive wiring trace, a first die including at least an integrated circuit, the first die being positioned above a portion of the flexible material, and an encapsulant material that covers the first die and at least a portion of the flexible material. A method is disclosed which includes positioning a first die above a portion of a flexible material, the first die including an integrated circuit and the flexible material including at least one conductive wiring trace, and forming an encapsulant material that covers the first die and at least a portion of the flexible material, wherein at least a portion of the flexible material extends beyond the encapsulant material.

Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.

Abstract: A semiconductor device package includes a carrier, one or more semiconductor devices on the carrier, and a redistribution element above the uppermost of the one or more semiconductor devices. The redistribution element includes an array of contact pads that communicate with each semiconductor device of the package. The package may also include an encapsulant through which the contact pads of the redistribution element are at least electrically exposed. Methods for assembling and packaging semiconductor devices, as well as methods for assembling multiple packages, including methods for replacing the functionality of one or more defective semiconductor devices of a package according to embodiments of the present invention, are also disclosed.

Abstract: A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A first of the conductive planes includes two sets of bond fingers, conductive traces that extend from a first set of the bond fingers, and two sets of redistributed bond pads, including a first set to which the conductive traces lead. The second conductive plane includes conductive traces that extend from locations that are opposite from the second set of bond fingers toward locations that are opposite from the locations of the second set of redistributed bond pads. Conductive vias are formed through the second set of bond fingers to the conductive traces of the second conductive plane. In addition, conductive vias are also formed to electrically connect the conductive vias of the second conductive plane to their corresponding redistributed bond pads in the first conductive plane.

Abstract: Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an integrated circuit chip comprising an exposed backside surface defining a plane, a plurality of wire bonds that are conductively coupled to the integrated circuit chip, each of the plurality of wire bonds being conductively coupled to a conductive exposed portion, a portion of the conductive exposed portion being positioned in the plane defined by the backside surface, and an encapsulant material positioned adjacent the integrated circuit chip and the plurality of wire bonds.

Abstract: Stacked microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. An embodiment of one such microelectronic device can include a support member and a first known good microelectronic die attached to the support member. The first die includes an active side, a back side opposite the active side, a first terminal at the active side, and integrated circuitry electrically coupled to the first terminal. The first die also includes a first redistribution structure at the active side of the first die. The microelectronic device can also include a second known good microelectronic die attached to the first die in a stacked configuration such that a back side of the second die is facing the support member and an active side of the second die faces away from the support member. The second die includes a second redistribution structure at the active side of the second die.