Patents by Inventor Chong-Gim Gan

Chong-Gim Gan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7672101
    Abstract: A system includes a driving device operating at first supply voltage Vdd1 and having a CMOS output. A driven devise operates at a second supply voltage Vdd2 lower than the first supply voltage Vdd1, and has a CMOS input with an NMOS pull-down transistor. A protection circuit includes a first resistor coupled to the CMOS output of the driving device and a gate of the NMOS pull-down transistor. A parasitic NPN bipolar junction transistor has a drain connected to the gate of the NMOS pull-down transistor sad a source coupled to a lower-voltage supply rail VSS. A second resistor connects a gate of the parasitic NPN bipolar junction transistor to Vss. The second resistor has a resistance sized for controlling a trigger voltage of the parasitic NPN bipolar junction transistor for protecting a gate oxide layer of the NMOS pull-down transistor from an electrostatic discharge.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: March 2, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shu-Huei Lin, Chong-Gim Gan, Yi-Hsun Wu, Yu-Chang Lin
  • Publication number: 20090067105
    Abstract: A system includes a driving device operating at first supply voltage Vdd1 and having a CMOS output. A driven devise operates at a second supply voltage Vdd2 lower than the first supply voltage Vdd1, and has a CMOS input with an NMOS pull-down transistor. A protection circuit includes a first resistor coupled to the CMOS output of the driving device and a gate of the NMOS pull-down transistor. A parasitic NPN bipolar junction transistor has a drain connected to the gate of the NMOS pull-down transistor sad a source coupled to a lower-voltage supply rail VSS. A second resistor connects a gate of the parasitic NPN bipolar junction transistor to Vss. The second resistor has a resistance sized for controlling a trigger voltage of the parasitic NPN bipolar junction transistor for protecting a gate oxide layer of the NMOS pull-down transistor from an electrostatic discharge.
    Type: Application
    Filed: September 10, 2007
    Publication date: March 12, 2009
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Huei Lin, Chong-Gim Gan, Yi-Hsun Wu, Yu-Chang Lin
  • Patent number: 7309897
    Abstract: An integrated circuit has functional circuitry coupled to a terminal. An electrostatic discharge protector can be coupled to the terminal to protect the functional circuitry from an electrostatic discharge. A substrate includes a first semiconductor material with a first dopant type. A plurality of drain segments adjoin the substrate. Each of the drain segments has a first conductor, a second conductor, and a third conductor. A central via set in a central region of the drain segment couples the second conductor to the third conductor. A peripheral via set in a peripheral region of the drain segment couples the first conductor to the second conductor. A plurality of source segments adjoin the substrate and laterally interlace with the drain segments.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: December 18, 2007
    Assignee: Taiwan Semiconductor Manuafacturing Company, Ltd.
    Inventors: Kuo-Feng Yu, Jian-Hsing Lee, Juing-Yi Wu, Chong-Gim Gan, Dun-Nian Yaung
  • Publication number: 20070241406
    Abstract: An integrated circuit has functional circuitry coupled to a terminal. An electrostatic discharge protector can be coupled to the terminal to protect the functional circuitry from an electrostatic discharge. A substrate includes a first semiconductor material with a first dopant type. A plurality of drain segments adjoin the substrate. Each of the drain segments has a first conductor, a second conductor, and a third conductor. A central via set in a central region of the drain segment couples the second conductor to the third conductor. A peripheral via set in a peripheral region of the drain segment couples the first conductor to the second conductor. A plurality of source segments adjoin the substrate and laterally interlace with the drain segments.
    Type: Application
    Filed: April 13, 2006
    Publication date: October 18, 2007
    Inventors: Kuo-Feng Yu, Jian-Hsing Lee, Juing-Yi Wu, Chong-Gim Gan, Dun-Nian Yaung