Abstract: In one embodiment, a plurality of kernels are provided. Each kernel may simulate a partition of a design under test. A plurality of event regions are provided. The regions may be in an ordered priority. Events for the device under test may be determined for event regions in each of the kernels. An event region to execute events in is then determined and all kernels may execute events in the same event region. Kernels then execute events for the determined event region. When finished executing events in an event queue, data synchronization may occur. In this case, information may be synced among kernels, such as status and state values for shared objected are synchronized.

Abstract: In one embodiment, a plurality of kernels are provided. Each kernel may simulate a partition of a design under test. A plurality of event regions are provided. The regions may be in an ordered priority. Events for the device under test may be determined for event regions in each of the kernels. An event region to execute events in is then determined and all kernels may execute events in the same event region. Kernels then execute events for the determined event region. When finished executing events in the event queue, data synchronization may occur. In this case, information may be synced among kernels, such as status and state values for shared objected are synchronized.

Abstract: A system and method for automated design verification. A test bench stimulates a simulated design with test vectors. A coverage analysis tool monitors output data from the simulated design and identifies portions of the simulated design that remain to be tested. A test generator produces and sends test vectors to the test bench which exercise (i.e., test) the portions of the simulated design that the coverage analysis tool has indicated still remain untested. In the method, a first step executes a simulated design on a test bench. A second step interprets the simulated design as if this design were a state diagram composed of a set of basic blocks interconnected by transition arcs. A third step generates test vectors to exercise some of the basic blocks and transition arcs. A fourth step reports the basic blocks and transition arcs which have not been tested. A fifth step generates a new set of test vectors to exercise the as yet untested basic blocks and transition arcs.

Abstract: To identify a finite state machine and verify a circuit design, the invention identifies, in a design description, a set of constructs, a construct in the set of constructs, and an object in the construct. It next identifies a first subset of constructs in the set of constructs which can control a change of a value of the object, and then identifies a second subset of constructs whose values can be changed directly or indirectly by the object. The identifying and storing steps are repeated for all objects in the construct and for all constructs in the set of constructs. A finite state machine is identified by searching for a first object which controls a change of a value of a second object and whose value is also changed directly or indirectly by the second object. This method of identifying finite state machine elements in a design description is used by a test generator which then generates test vectors for exercising the finite state machine elements on a test bench.

Abstract: A system and method for automated design verification. A test bench stimulates a simulated design with test vectors. A coverage analysis tool monitors output data from the simulated design and identifies portions of the simulated design that remain to be tested. A test generator produces and sends test vectors to the test bench which exercise (i.e., test) the portions of the simulated design that the coverage analysis tool has indicated still remain untested. In the method, a first step executes a simulated design on a test bench. A second step interprets the simulated design as if this design were a state diagram composed of a set of basic blocks interconnected by transition arcs. A third step generates test vectors to exercise some of the basic blocks and transition arcs. A fourth step reports the basic blocks and transition arcs which have not been tested. A fifth step generates a new set of test vectors to exercise the as yet untested basic blocks and transition arcs.