Patents by Inventor Chong H. Lee
Chong H. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140009188Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).Type: ApplicationFiled: September 10, 2013Publication date: January 9, 2014Applicant: Altera CorporationInventors: Toan Thanh Nguyen, Thungoc M. Tran, Sergey Shumarayev, Arch Zaliznyak, Shoujun Wang, Ramanand Venkata, Chong H. Lee
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Publication number: 20130265179Abstract: Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.Type: ApplicationFiled: May 31, 2013Publication date: October 10, 2013Inventors: Ramanand Venkata, Chong H. Lee
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Patent number: 8477831Abstract: An interface for use in a local device includes a transmitter portion programmably configurable to at least three data rates, a receiver portion programmably configurable to those at least three data rates, and an automatic speed negotiation module operatively connected to the transmitter portion and the receiver portion to configure the transmitter portion and the receiver portion for communication with a remote device at a single data rate that is a best available one of those at least three data rates. The date rate can be adjusted by adjusting transmitter data path width and receiver data path width, adjusting a frequency of said transmitter data path and said receiver data path, and oversampling. Byte serialization or deserialization can be enabled or disabled to alter the width of the data, depending on the data rate, for transfer to/from the remainder of the local device.Type: GrantFiled: August 20, 2010Date of Patent: July 2, 2013Assignee: Altera CorporationInventors: Divya Vijayaraghavan, Chong H. Lee
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Patent number: 8462908Abstract: Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.Type: GrantFiled: December 21, 2010Date of Patent: June 11, 2013Assignee: Altera CorporationInventors: Ramanand Venkata, Chong H. Lee
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Patent number: 8458383Abstract: On programmable device, each layer of a programmable interface, for a protocol which has a protocol stack including at least a physical layer, a data link layer and a transaction layer, is selectably bypassable. When a layer is bypassed, all other layers downstream of that layer also are bypassed. In addition, the interface may be divided into different clock domains running at different clock rates, reflecting clock rates within the programmable device and outside the programmable device. Layers may be bypassed to allow a user to substitute a custom layer in programmable logic, or to substitute an updated layer for debugging purposes.Type: GrantFiled: August 30, 2007Date of Patent: June 4, 2013Assignee: Altera CorporationInventors: Curt Wortman, Chong H. Lee, Divya Vijayaraghavan, Ning Xue
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Patent number: 8363770Abstract: Systems, methods, and circuits extract data from an oversampled data stream in the presence of noise and/or jitter. Pointers decide which data samples of the oversampled data stream are extracted. Some of the pointers occurring right after a data transition are positioned based on the location of previous pointers, rather than using the data transition points as occurs during an alignment. Settings such as the frequency of how often a pointer is aligned with a data transition and a maximum adjustment amount during an alignment may be programmable.Type: GrantFiled: November 1, 2006Date of Patent: January 29, 2013Assignee: Altera CorporationInventors: Ning Xue, Chong H. Lee
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Publication number: 20120307878Abstract: An interface for use in a local device includes a transmitter portion programmably configurable to at least three data rates, a receiver portion programmably configurable to those at least three data rates, and an automatic speed negotiation module operatively connected to the transmitter portion and the receiver portion to configure the transmitter portion and the receiver portion for communication with a remote device at a single data rate that is a best available one of those at least three data rates. The date rate can be adjusted by adjusting transmitter data path width and receiver data path width, adjusting a frequency of said transmitter data path and said receiver data path, and oversampling. Byte serialization or deserialization can be enabled or disabled to alter the width of the data, depending on the data rate, for transfer to/from the remainder of the local device.Type: ApplicationFiled: August 20, 2010Publication date: December 6, 2012Applicant: ALTERA CORPORATIONInventors: Divya Vijayaraghavan, Chong H. Lee
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Patent number: 8291255Abstract: Clock data recovery (CDR) circuitry of a high-speed serial interface on a programmable integrated circuit device toggles, during the electrical idle period of the receiver of the interface, between its “lock-to-reference” (“LTR”) state and its normal “lock-to-data” (“LTD”) state. Whenever during this toggling mode the CDR circuitry toggles to the LTD state, it remains in that state for a predetermined interval and then returns to the LTR state, unless, while it is in the LTD state, it receives a signal from elsewhere in the receiver that data have been received and byte synchronization has occurred. The predetermined toggling interval preferably is long enough to obtain an LTR lock to minimize frequency drift, but short enough to avoid unnecessary delay in detection of the synchronization signal. Preferably, this interval is programmable by the user within limits determined by the characterization of the programmable device. Unreliable analog signal detection is thereby avoided.Type: GrantFiled: April 7, 2011Date of Patent: October 16, 2012Assignee: Altera CorporationInventors: Divya Vijayaraghavan, Michael Menghui Zheng, Lana May Chan, Chong H. Lee
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Patent number: 8165191Abstract: Embodiments in the disclosure include a multi-protocol transceiver including a configurable arrangement of receive and/or transmit circuitry. An exemplary transceiver can be selectively configured to effectively transmit and/or receive data communications corresponding to a select one of a plurality of high-speed communication protocols. Another more particular embodiment disclosed includes a configurable data path through link-wide Physical Coding Sub-layer (“PCS”) circuitry including link-wide clock compensation, encoding/decoding, and scrambling/descrambling circuitry and lane striping/de-striping circuitry; the configurable data path further includes lane-wide circuitry including clock compensation, encoding/decoding, receive block sync, and Physical Medium Access sub-layer (“PMA”) circuitry, and further includes bit muxing/de-muxing circuitry coupled to Physical Medium Dependent (“PMD”) sub-layer circuitry.Type: GrantFiled: October 17, 2008Date of Patent: April 24, 2012Assignee: Altera CorporationInventors: Divya Vijayaraghavan, Curt Wortman, Chong H. Lee
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Patent number: 8098087Abstract: A method and apparatus is provided for standby voltage offset cancellation at inputs to a comparator within a receiver channel. Each of a first comparator input and second comparator input is isolated from an input signal such that each of the first and second comparator inputs attains a respective standby voltage level. A voltage level on one of the first and second comparator inputs is incrementally changed, while the output signal of the comparator is monitored. Upon detecting a state transition in the output signal of the comparator, the incremental changing of the voltage level on the one comparator input is stopped at a final voltage level setting. The final voltage level setting is stored in a computer memory for reference in setting of the voltage level at the one comparator input so as to compensate for the standby voltage offset at the inputs to the comparator.Type: GrantFiled: March 5, 2007Date of Patent: January 17, 2012Assignee: Altera CorporationInventors: John Dung-Ngoc Lam, Arch Zaliznyak, Wilson Wong, Tin H. Lai, Chong H. Lee, Sergey Shumarayev
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Publication number: 20110211621Abstract: High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.Type: ApplicationFiled: May 9, 2011Publication date: September 1, 2011Applicant: ALTERA CORPORATIONInventors: Sergey Shumarayev, Bill W. Bereza, Chong H. Lee, Rakesh H. Patel, Wilson Wong
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Patent number: 7984209Abstract: Interface circuitry that is used to interface data between two different clock regimes that may have somewhat different speeds includes the ability to determine which of the clock regimes is faster. Depending on which clock regime is found to be faster, the baseline (nominal difference between data write and data read addresses of a FIFO memory in the interface circuitry) is shifted (i.e., toward the full or empty condition of the FIFO, as is appropriate for which of the clock regimes has been found to be faster). Adjustments may also be made to the threshold(s) used for such purposes as character insertion/deletion and overflow/underflow indication. This technique may allow use of a smaller FIFO and reduce latency of the interface circuitry.Type: GrantFiled: December 12, 2006Date of Patent: July 19, 2011Assignee: Altera CorporationInventors: Vinson Chan, Michael Menghui Zheng, Chong H. Lee
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Patent number: 7940814Abstract: High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.Type: GrantFiled: October 9, 2009Date of Patent: May 10, 2011Assignee: Altera CorporationInventors: Sergey Shumarayev, Bill W. Bereza, Chong H. Lee, Rakesh H. Patel, Wilson Wong
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Publication number: 20110090101Abstract: Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.Type: ApplicationFiled: December 21, 2010Publication date: April 21, 2011Inventors: Ramanand Venkata, Chong H. Lee
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Patent number: 7925913Abstract: Clock data recovery (CDR) circuitry of a high-speed serial interface on a programmable integrated circuit device toggles, during the electrical idle period of the receiver of the interface, between its “lock-to-reference” (“LTR”) state and its normal “lock-to-data” (“LTD”) state. Whenever during this toggling mode the CDR circuitry toggles to the LTD state, it remains in that state for a predetermined interval and then returns to the LTR state, unless, while it is in the LTD state, it receives a signal from elsewhere in the receiver that data have been received and byte synchronization has occurred. The predetermined toggling interval preferably is long enough to obtain an LTR lock to minimize frequency drift, but short enough to avoid unnecessary delay in detection of the synchronization signal. Preferably, this interval is programmable by the user within limits determined by the characterization of the programmable device. Unreliable analog signal detection is thereby avoided.Type: GrantFiled: September 18, 2007Date of Patent: April 12, 2011Assignee: Altera CorporationInventors: Divya Vijayaraghavan, Michael Menghui Zheng, Lana May Chan, Chong H. Lee
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Patent number: 7869553Abstract: Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.Type: GrantFiled: August 20, 2004Date of Patent: January 11, 2011Assignee: Altera CorporationInventors: Ramanand Venkata, Chong H Lee
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Patent number: 7869343Abstract: A field-programmable gate array (“FPGA”) or programmable logic device (“PLD”) includes relatively general-purpose PLD core circuitry and relatively specialized high-speed serial interface (“HSSI”) hard IP circuitry. To better support applications that include forward error correction (“FEC”), some tasks related to FEC (e.g., FIFO operations) are performed in the PLD core circuitry, while other FEC tasks (e.g., FEC calculations) are performed in the HSSI hard IP circuitry.Type: GrantFiled: June 5, 2006Date of Patent: January 11, 2011Assignee: Altera CorporationInventors: Ning Xue, Chong H. Lee
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Publication number: 20100277201Abstract: An integrated circuit (IC) is provided. The IC includes a first region having an array of programmable logic cells. The IC also includes a second region incorporated into the IC and in communication with the first region. The second region includes standard logic cells and base cells. In one embodiment, the standard logic cells are assembled or interconnected to accommodate known protocols. The base cells include configurable logic to adapt to modifications to emerging communication protocols, which are supported by the base cells. The second region can be embedded in the first region in one embodiment. In another embodiment, the second region is defined around a perimeter of the first region. The configurable logic may be composed of hybrid logic elements that have metal mask programmable interconnections so that as emerging communication protocols evolve and are modified, the IC can be modified to accommodate to the changes in the protocol.Type: ApplicationFiled: May 1, 2009Publication date: November 4, 2010Inventors: Curt Wortman, Chong H. Lee, Richard G. Cliff
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Publication number: 20100215086Abstract: Embodiments in the disclosure include a multi-protocol transceiver including a configurable arrangement of receive and/or transmit circuitry. An exemplary transceiver can be selectively configured to effectively transmit and/or receive data communications corresponding to a select one of a plurality of high-speed communication protocols. Another more particular embodiment disclosed includes a configurable data path through link-wide Physical Coding Sub-layer (“PCS”) circuitry including link-wide clock compensation, encoding/decoding, and scrambling/descrambling circuitry and lane striping/de-striping circuitry; the configurable data path further includes lane-wide circuitry including clock compensation, encoding/decoding, receive block sync, and Physical Medium Access sub-layer (“PMA”) circuitry, and further includes bit muxing/de-muxing circuitry coupled to Physical Medium Dependent (“PMD”) sub-layer circuitry.Type: ApplicationFiled: October 17, 2008Publication date: August 26, 2010Applicant: Altera CorporationInventors: Divya Vijayaraghavan, Curt Wortman, Chong H. Lee
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Patent number: 7724598Abstract: A megafunction block is provided that includes a serial interface enabling a user to specify settings of a configurable block of a programmable logic device. The megafunction block includes a register array having the capability of translating address information into actual addresses for a memory of the configurable block. Thus, as future configurations/standards are developed that a programmable logic device with the megafunction block will interfaces with, the settings for interfacing with the standards may be added to the register array. Consequently, the pin count will not need to increase as the megafunction block is scalable through the register map. Control logic verifies that the translated address is a valid address and the control logic will generate a selection signal based on whether a read or write operation is to be performed.Type: GrantFiled: April 19, 2007Date of Patent: May 25, 2010Assignee: Altera CorporationInventors: Vinson Chan, Chong H. Lee, Binh Ton, Thiagaraja Gopalsamy, Marcel A. LeBlanc, Neville Carvalho