Patents by Inventor Chong Ho CHO

Chong Ho CHO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9668344
    Abstract: A semiconductor package may include a first substrate including a first connection portion disposed on a surface of the first substrate and a second substrate including a second connection portion disposed on a surface of the second substrate. The second substrate may be disposed over the first substrate and the second connection portion facing the first connection portion. A first connection loop portion may be provided to include an end connected to the first connection portion. A second connection loop portion may be provided to include one end connected to the second connection portion and the other end combined with the first connection loop portion.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: May 30, 2017
    Assignee: SK hynix Inc.
    Inventors: Won Duck Jung, Jong Ho Lee, Joo Hyun Kang, Chong Ho Cho, In Chul Hwang
  • Publication number: 20160316559
    Abstract: A semiconductor package may include a first substrate including a first connection portion disposed on a surface of the first substrate and a second substrate including a second connection portion disposed on a surface of the second substrate. The second substrate may be disposed over the first substrate and the second connection portion facing the first connection portion. A first connection loop portion may be provided to include an end connected to the first connection portion. A second connection loop portion may be provided to include one end connected to the second connection portion and the other end combined with the first connection loop portion.
    Type: Application
    Filed: October 8, 2015
    Publication date: October 27, 2016
    Inventors: Won Duck JUNG, Jong Ho LEE, Joo Hyun KANG, Chong Ho CHO, In Chul HWANG
  • Patent number: 9397757
    Abstract: A semiconductor package includes a package substrate, a first semiconductor substrate and a second semiconductor substrate stacked on the package substrate, and an optical transceiver that generates and receives an optical signal travelling between the package substrate and the second semiconductor substrate using an infrared (IR) ray that passes through the first semiconductor substrate.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: July 19, 2016
    Assignee: SK HYNIX INC.
    Inventors: In Chul Hwang, Il Hwan Cho, Ki Young Kim, Kyoung Mo Yang, Jae Joon Ahn, Chong Ho Cho
  • Publication number: 20150222364
    Abstract: A semiconductor package includes a package substrate, a first semiconductor substrate and a second semiconductor substrate stacked on the package substrate, and an optical transceiver that generates and receives an optical signal travelling between the package substrate and the second semiconductor substrate using an infrared (IR) ray that passes through the first semiconductor substrate.
    Type: Application
    Filed: June 27, 2014
    Publication date: August 6, 2015
    Inventors: In Chul HWANG, Il Hwan CHO, Ki Young KIM, Kyoung Mo YANG, Jae Joon AHN, Chong Ho CHO
  • Patent number: 9093441
    Abstract: The semiconductor package includes an upper semiconductor chip stacked on a package substrate and a support layer or a lower semiconductor chip disposed between the upper semiconductor chip and the package substrate. The upper semiconductor chip includes a protrusion downwardly extending from an edge thereof. The protrusion of the upper semiconductor chip is combined with a sidewall of the support layer or the lower semiconductor chip. Related methods are also provided.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: July 28, 2015
    Assignee: SK Hynix Inc.
    Inventors: Ji Eun Kim, Cheol Ho Joh, Hee Min Shin, Kyu Won Lee, Chong Ho Cho
  • Patent number: 8951810
    Abstract: Methods of forming an interconnection line pattern using a screen printing technique. The method includes preparing a substrate having unevenness, aligning a stencil mask on the substrate, and printing a paste including materials for forming the interconnection line pattern on a convex portion of the unevenness formed on the substrate.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: February 10, 2015
    Assignee: SK hynix Inc.
    Inventors: Kyu Won Lee, Cheol Ho Joh, Ji Eun Kim, Hee Min Shin, Chong Ho Cho
  • Publication number: 20140175638
    Abstract: The semiconductor package includes an upper semiconductor chip stacked on a package substrate and a support layer or a lower semiconductor chip disposed between the upper semiconductor chip and the package substrate. The upper semiconductor chip includes a protrusion downwardly extending from an edge thereof. The protrusion of the upper semiconductor chip is combined with a sidewall of the support layer or the lower semiconductor chip. Related methods are also provided.
    Type: Application
    Filed: March 18, 2013
    Publication date: June 26, 2014
    Applicant: SK HYNIX INC.
    Inventors: Ji Eun KIM, Cheol Ho JOH, Hee Min SHIN, Kyu Won LEE, Chong Ho CHO
  • Publication number: 20140057369
    Abstract: Methods of forming an interconnection line pattern using a screen printing technique. The method includes preparing a substrate having unevenness, aligning a stencil mask on the substrate, and printing a paste including materials for forming the interconnection line pattern on a convex portion of the unevenness formed on the substrate.
    Type: Application
    Filed: December 18, 2012
    Publication date: February 27, 2014
    Applicant: SK hynix Inc.
    Inventors: Kyu Won LEE, Cheol-Ho JOH, Ji Eun KIM, Hee-Min SHIN, Chong Ho CHO