Abstract: An electronics packaging system includes an insulator that electrically insulates a heat sink from electrical leads. An interface between the insulator and the heat sink includes a stress reliever constructed such that a stiffness of the interface is greater than the stiffness of the interface without the stress reliever.

Abstract: An electronics packaging system includes an insulator that electrically insulates a heat sink from electrical leads. An interface between the insulator and the heat sink includes a stress reliever constructed such that a stiffness of the interface is greater than the stiffness of the interface without the stress reliever.

Abstract: RF feedthroughs for use with monolithic microwave integrated circuits (MMIC) are installed in environmentally protective or hermetically sealed packages that provide electromagnetic shielding. A feedthrough for an MMIC package has a dielectric substrate, a microstrip or transmission line formed on the substrate for transmitting high frequency electronic signals and a wall disposed above the transmission line and the substrate. The wall of the feedthrough has a varying thickness so that the narrowest portion of the wall is disposed on the transmission line substantially perpendicular to the substrate. The transmission line also has a varying width so that the narrowest width portion of the transmission line crosses the narrowest portion of the wall. The narrowest portion of the wall may be created by placing two oppositely facing concaved surfaces on each side of the wall. To reduce parasitic capacitance, the substrate and the wall may each have an air cavity embedded in respective bodies.

Abstract: A hermetically sealed package assembly for microwave circuits in the high microwave frequencies having a dielectric gap defined in the substrate. The package assembly comprises a substrate for carrying the circuit on a top surface, a seal ring wall carried on the top surface, a via structure provided through the substrate for transmitting high-frequency signals into and out of the package, and a conducive lead carried on the bottom surface of the substrate and passes under the seal ring wall. A dielectric gap is provided in the substrate between the seal ring wall and the lead to reduce the capacitive coupling between the lead and the wall. The gap may be a sealed cavity provided inside the substrate, or a cutout area in the substrate so that the lead is suspended in air at the location where it passes under the seal ring wall.

Abstract: A ceramic chip-resistant chamfered integrated circuit package and an apparatus for and method of manufacture thereof. The exposed-surface edge of each short end of a ceramic package component (base and/or cap) are made with an integral chamfer at an angle of from about 20.degree. to about 85.degree. relative to the plane of the opposing inner surface of the component. The height H of the chamfer is from about 20% to about 67% of the thickness T of the ceramic package component. In particular, the preferred angle of the chamfer is from about 50.degree. to about 70.degree., with a preferred height H of about 30% to about 50% of the thickness T. The integral chamfer of each ceramic package component is made by means of an inventive die-press apparatus for inverted formation of the ceramic package component. The inventive method forms the chamfers without causing localized compaction of the ceramic powder starting material.

Abstract: A partially coated assembly structure and a method for making a ceramic lid for a hermetically sealed package for an EPROM circuit are disclosed. The assembly structure includes, in combination, a ceramic lid, a UV transparent lens, and two fixtures for supporting the lens in the lid. The two fixtures are coated with a non-lens wetting film in predetermined areas where contact is made between the fixtures and the lens, and between the fixtures and the lid. The UV transparent lens is hermetically sealed to the ceramic lid by firing the assembly structure. The assembly structure prevents the lens from attracting foreign particulate matter during firing, thereby leaving the surfaces of the lens clean. The method provides a ceramic lid having a UV transparent lens hermetically sealed thereto, which finds wide use in integrated circuit packages for high-density EPROM's because of the untainted surfaces of the lens.

Abstract: A ceramic chip-resistant chamfered integrated circuit package and an apparatus for and method of manufacture thereof. The exposed-surface edge of each short end of a ceramic package component (base and/or cap) are made with an integral chamfer at an angle of from about 20.degree. to about 85.degree. relative to the plane of the opposing inner surface of the component. The height H of the chamfer is from about 20% to about 67% of the thickness T of the ceramic package component. In particular, the preferred angle of the chamfer is from about 50.degree. to about 70.degree., with a preferred height H of about 30% to about 50% of the thickness T. The integral chamfer of each ceramic package component is made by means of an inventive die-press apparatus for inverted formation of the ceramic package component. The inventive method forms the chamfers without causing localized compaction of the ceramic powder starting material.