Patents by Inventor Chong Kwon

Chong Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070132522
    Abstract: Provided is an LC resonance voltage-controlled oscillator (VCO) used for a multi-band multi-mode wireless transceiver. In order to generate a multi-band frequency, a capacitor bank and a switchable inductor are included in the LC resonance voltage-controlled oscillator. The LC resonance voltage-controlled oscillator employs an adjustable emitter-degeneration negative resistance cell in place of tail current sources in order to compensate for non-uniform oscillation amplitude caused by the capacitor bank and prevent the degradation of a phase noise due to the tail current sources.
    Type: Application
    Filed: October 2, 2006
    Publication date: June 14, 2007
    Inventors: Ja Lee, Kwi Kim, Chong Kwon, Jong Kim, Sang Lee, Kyoung Cho
  • Publication number: 20070132515
    Abstract: A wide-band multimode frequency synthesizer using a Phase Locked Loop (PLL) is provided. The multiband frequency synthesizer includes a multimode prescaler, a phase detector/a charge pump, a swallow type frequency divider, and a switching bank LC tuning voltage-controlled oscillator having wide-band and low phase noise characteristics. The multimode prescaler operates in five modes and divides a signal up to 12 GHz. The wide-band frequency synthesizer can be used in various fields such as WLAN/HYPERLAN/DSRC/UWB systems that operate in the frequency range from 2 GHz to 9 GHz.
    Type: Application
    Filed: December 5, 2006
    Publication date: June 14, 2007
    Inventors: Ja Lee, Kwi Kim, Chong Kwon, Jong Kim, Sang Lee
  • Publication number: 20070131965
    Abstract: An ESD protection device with a silicon controlled rectifier (SCR) structure which is applied to a nano-device-based high-speed I/O interface circuit and semiconductor substrate operated by a low power voltage. The triple-well low-voltage-triggered ESD protection device includes: a deep n-type well formed on a p-type substrate; n- and p-type wells formed to be mutually connected in the deep n-type well; and a bias application region for applying a direct bias voltage to the p-type well.
    Type: Application
    Filed: December 7, 2006
    Publication date: June 14, 2007
    Inventors: Kwi Kim, Chong Kwon, Jong Kim, Young Koo
  • Publication number: 20060125054
    Abstract: Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC).
    Type: Application
    Filed: December 13, 2005
    Publication date: June 15, 2006
    Inventors: Kwi Kim, Chong Kwon, Jong Kim
  • Publication number: 20060125670
    Abstract: Provided are a current cell and digital-to-analog converter (DAC) using the same. The current cell includes a current source; a first transistor transmitting a current produced from the current source to a first output node based on a first signal; a second transistor transmitting a current produced from the current source to a second output node based on a second signal; a first capacitor coupled between a gate of the first transistor and the second output node; and a second capacitor coupled between a gate of the second transistor and the first output node. A current mode DAC can improve in dynamic performance by using a plurality of current cells each having the above-described configuration.
    Type: Application
    Filed: October 18, 2005
    Publication date: June 15, 2006
    Inventors: Min Cho, Seung Lee, Chong Kwon, Jong Kim
  • Publication number: 20060125016
    Abstract: Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well corresponding to a substrate of a ggNMOS device. Thus, a trigger voltage of the SCR is reduced. In addition, two discharge paths are formed using two SCRs comprised of PNP and NPN bipolar transistors, with the result that the ESD protection circuit can have great discharge capacity.
    Type: Application
    Filed: December 5, 2005
    Publication date: June 15, 2006
    Inventors: Kwi Kim, Chong Kwon, Jong Kim
  • Publication number: 20060125460
    Abstract: Provided is a low-reference-current generator that includes a circuit employing two feedback loops enabling it to operate even at a low voltage, has a high power supply rejection ratio (PSRR) to control power supply noise, and simply forms a voltage without a voltage-to-current converter used in a conventional general reference current generator. The reference current generator includes: a first voltage generator receiving a predetermined current and generating a first voltage that decreases as temperature increases; a second voltage generator generating a second voltage that increases as temperature increases; a first current generator generating a first current corresponding to the first voltage; a second current generator generating a second current corresponding to the second voltage; and a reference current generator receiving the first current and the second current and generating a reference current that is the sum of the first current and the second current.
    Type: Application
    Filed: December 9, 2005
    Publication date: June 15, 2006
    Inventors: Bong Mheen, Min Cho, Chong Kwon, Jin Kang