Patents by Inventor Chong Leong Gan

Chong Leong Gan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240071963
    Abstract: A semiconductor device assembly is provided. The assembly includes a package substrate which has a tunneled interconnect structure. The tunneled interconnect structure has a solder-wettable surface, an interior cavity, and at least one microvia extending from the surface to the cavity. The assembly further includes a semiconductor device disposed over the substrate and a solder joint coupling the device and the substrate. The joint comprises the solder between the semiconductor device and the interconnect structure, which includes the solder on the surface, the solder in the microvia, and the solder within the interior cavity.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: Yun Ting Hsu, Chong Leong Gan, Min Hua Chung, Yung Sheng Zou
  • Publication number: 20240071977
    Abstract: A semiconductor package having a fillet is provided. The semiconductor package includes a trace disposed within a solder mask that has a top surface. A first die is over the solder mask and mechanically couples with the trace. A first adhesive is between the trace and the first die where sides of the first die and the first adhesive define a die edge. The semiconductor package includes a fillet adjacent the die edge and a second die above the first die. The semiconductor package also includes a second adhesive having a bottom surface where the second adhesive is between the first die and the second die. The solder mask top surface, the first die surface, and the second adhesive bottom surface define a cavity where the fillet is within the cavity at the die edge.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Chen Yu Huang, Chong Leong Gan
  • Publication number: 20230387079
    Abstract: Radiation hard semiconductor devices and packaging are disclosed. A semiconductor device assembly includes a substrate, a semiconductor die stack electrically coupled to the substrate, and an ionizing radiation shield disposed over a top die of the semiconductor die stack, wherein the ionizing radiation shield comprises silicon carbide (SiC). The semiconductor device assembly further includes an encapsulant at least partially encapsulating the semiconductor die stack and the ionizing radiation shield.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Inventor: Chong Leong Gan
  • Publication number: 20230268318
    Abstract: Systems and methods for measuring and predicting the strength of semiconductor devices and packaging are disclosed. In some embodiments, a semiconductor device assembly comprises a package substrate, a semiconductor die electrically coupled to the package substrate, and a molding covering at least a portion of the semiconductor die, where the molding includes a through-mold via (TMV) extending from an upper surface into the mold material to a depth. The semiconductor device assembly can include a strain gauge disposed in the molding at the depth of the TMV and be electrically coupled to the TMV. For example, the TMV can extend to the surface of the semiconductor die, to the package substrate, or other critical areas of the semiconductor device assembly, enabling strain to be measured at these depths. The semiconductor device assembly can be used in testing to predict the strength of the die and packaging in real-world scenarios, such as being dropped, bent, or crushed.
    Type: Application
    Filed: February 18, 2022
    Publication date: August 24, 2023
    Inventors: Chien Ming Chen, Shams U. Arifeen, Chong Leong Gan, Christopher Glancey
  • Publication number: 20230207403
    Abstract: A semiconductor device assembly includes a substrate and a first semiconductor device mounted to the substrate. An epoxy-based spacer is mounted to the substrate proximate to the first semiconductor device by an adhesive attached to a bottom surface of the epoxy-based spacer and to the substrate. A second semiconductor device is mounted directly to top surfaces of both the first semiconductor device and the epoxy-based spacer.
    Type: Application
    Filed: October 27, 2022
    Publication date: June 29, 2023
    Inventors: Li Jao, Min Hua Chung, Chong Leong Gan
  • Publication number: 20230062160
    Abstract: Semiconductor devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor devices include a package substrate, a stack of dies carried by the package substrate, and one or more radiation shields configured to absorb neutrons from neutron radiation incident on the semiconductor device. The radiation shields can include one or more walls attached to a perimeter portion of the package substrate at least partially surrounding the stack of dies and/or a lid carried over the stack of dies. Each of the radiation shields can include hydrocarbon materials, boron, lithium, gadolinium, cadmium, and like materials that effectively absorb neutrons from neutron radiation. In some embodiments, the semiconductor devices also include a molding material over the stack of dies and the radiation shields, and a hydrocarbon coating over an external surface of the mold material.
    Type: Application
    Filed: April 11, 2022
    Publication date: March 2, 2023
    Inventors: Chong Leong Gan, Min Hua Chung, Yung Sheng Zou, Lu Fu Lin, Li Jao
  • Patent number: 11515222
    Abstract: Semiconductor devices having flow controllers configured to reduce mitigation of mold material between stacked layers, and associated systems and methods, are disclosed herein. In some embodiments, the semiconductor device includes a package substrate that has first and second surfaces. First and second die stacks are formed on the first surface and are adjacent to each other. A portion of the first surface extends between the first and second die stacks. A layer of material is adhered to top surfaces of the first and second die stacks and extends at a distance above the package substrate to form a tunnel between the layer of material, opposing sidewalls of the die stacks, and the package substrate. The semiconductor device further includes a flow controller that is adhered to at least a portion of the first surface inside the tunnel that reduces a cross-sectional surface area of at least a portion of the tunnel.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: November 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Lu Fu Lin, Yung Sheng Zou, Chong Leong Gan, Li Jao, Min Hua Chung
  • Publication number: 20220208625
    Abstract: Semiconductor devices having flow controllers configured to reduce mitigation of mold material between stacked layers, and associated systems and methods, are disclosed herein. In some embodiments, the semiconductor device includes a package substrate that has first and second surfaces. First and second die stacks are formed on the first surface and are adjacent to each other. A portion of the first surface extends between the first and second die stacks. A layer of material is adhered to top surfaces of the first and second die stacks and extends at a distance above the package substrate to form a tunnel between the layer of material, opposing sidewalls of the die stacks, and the package substrate. The semiconductor device further includes a flow controller that is adhered to at least a portion of the first surface inside the tunnel that reduces a cross-sectional surface area of at least a portion of the tunnel.
    Type: Application
    Filed: December 31, 2020
    Publication date: June 30, 2022
    Inventors: Lu Fu Lin, Yung Sheng Zou, Chong Leong Gan, Li Jao, Min Hua Chung