Abstract: Rendering a graphical representation of an integrated circuit can include determining, using a processor, a tile of a device model at least partially within a viewport, determining, using the processor, an owning tile having a fly-over wire passing over the tile, determining, using the processor, a predetermined shape of the fly-over wire, and drawing, using the processor, the fly-over wire within the viewport based upon the shape.

Abstract: A system for graphics generation includes a processor configured to implement a modeling process and a GUI process. The modeling process is configured to generate a first graphics model including a plurality of objects. Each object defines a respective graphical depiction for a respective element of a programmable IC. The modeling process is also configured to serialize objects of the first graphics model according to a first application programming interface (API) definition file to produce a serialized graphics model. The GUI process is configured to, in response to receiving one or more objects of the serialized graphics model, deserialize the one or more objects of the serialized graphics model according to the first API definition file to produce a second graphics model. The GUI process is further configured to render the one or more objects of the second graphics model.

Abstract: A method is provided for communicating data between a first process and a second process. A set of inter-process functions of the first and second processes is determined. The set includes one or more functions of the first and second processes that are accessible by the other one of the first and second processes. An API definition file is generated. The API definition file includes a plurality of objects that each define a request to execute one or more inter-process functions of the set of inter-process functions. In response to input to the first process indicating a plurality of the inter-process functions, the plurality of inter-process functions are serialized according to the API definition file. The serialized set of functions is provided to the second process, using an FFI process, and deserialized according to the API definition file.

Abstract: A method of compressing data can include forming at least one container by grouping calls of data according to at least one data element of each call. The method can include arranging, via the processor, calls of the at least one container into a plurality of segments according to a minimal coordinate set and extracting common coordinates corresponding to a first coordinate type from the plurality of segments. Coordinates of a second coordinate type of each segment of the at least one container can be replaced with a segment start coordinate and first distance information specifying the coordinates of the second coordinate type. The common coordinates of the at least one container can be replaced with a common start coordinate and second distance information.

Abstract: A bioproduction process of preparing an hydrolysate from squid processing byproducts. The process includes obtaining squid byproducts and hydrolyzing the byproducts. The hydrolyzed product are heated until the viscosity stabilizes. The hydrolyzed product is then filtered to form a filtrate and then concentrated to form the desired hydrolysate.

Abstract: A method of assigning logic functions to macrocells assures that a maximum number of macrocells are assigned two or more logic functions. A first logic function is assigned to a macrocell without restriction. Rules are then applied to the macrocell to determine whether a second logic function may be assigned to the macrocell, and, if so, whether any restrictions exist on what the second logic function may be.

Abstract: An improved, high density CPLD includes a plurality of macrocell sections. Each macrocell section can receive a relatively large number of independent input terms and can generate as a base cluster, at least as many as 5 different product term signals (PT's) therefrom. Part or all of the macrocell's local 5 PT's may be used for generating a local sum-of-products (SoP) signal in a local, first-level ORring operation. Additionally SoP's generated in neighboring macrocell sections may be selectively and incrementally cascaded (cross-laced) for supplemental summing into the local SoP signal. SoP signals of neighboring sections may be further selected in a sums sharing array for second level summing. The combination of the first-level cascading (cross-lacing) and second-level sums sharing provides a wide range of programmably selectable granulations including that of having relatively fast generation of a sum of just a few PT's (e.g.

Abstract: An improved, high density CPLD includes a plurality of macrocell sections. Each macrocell section can receive a relatively large number of independent input terms and can generate as a base cluster, at least as many as 5 different product term signals (PT's) therefrom. Part or all of the macrocell's local 5 PT's may be used for generating a local sum-of-products (SoP) signal in a local, first-level ORring operation. Additionally SoP's generated in neighboring macrocell sections may be selectively and incrementally cascaded (cross-laced) for supplemental summing into the local SoP signal. SoP signals of neighboring sections may be further selected in a sums sharing array for second level summing. The combination of the first-level cascading (cross-lacing) and second-level sums sharing provides a wide range of programmably selectable granulations including that of having relatively fast generation of a sum of just a few PT's (e.g.

Abstract: An improved CPLD includes a plurality of macrocell modules (MM's) where each MM can receive a relatively large number of independent inputs (at least 80) and can generate at least 5 different product term signals (PT's) therefrom. All 5 PT's may be used for generating a local sum-of-products (SoP). Any of the 5 PT's may be stolen (steered-away) to instead provide a local control for its macrocell module. Each module includes a local SoS-producing gate that can produce a sums-of-sums signal (SoS) that represents a Boolean sum of one or more of the local SoP signal, of SoP signals of neighboring macrocell modules, and of SoS signals of neighboring macrocell modules. Simple allocation and super-allocation may be used to produce sums-of-sums signals of relatively large, one-pass function depth, such as 160PT's in one pass.