Abstract: The present invention relates to a high-speed motion compensation apparatus and method. The high-speed motion compensation apparatus for H.264/AVC includes a bus interface unit for reading a plurality of word addresses from an external storage device, aligning the reference pixels arranged over the plurality of word addresses, temporarily storing the aligned reference pixels, and sequentially outputting the aligned and temporarily stored reference pixels. A buffer unit temporarily stores overlapping reference pixels, which are repeatedly used to generate the sub-pixels, among the reference pixels output from the bus interface unit. An interpolation unit generates first half pixels, second half pixels, first quarter pixels, and second quarter pixels, using the reference pixels output from the bus interface unit. A chroma filter unit generates chrome pixels using the reference pixels output from the bus interface unit.

Abstract: The present invention relates to a high-speed motion compensation apparatus and method. The high-speed motion compensation apparatus for H264/AVC includes a bus interface unit for reading a plurality of word addresses from an external storage device, aligning the reference pixels arranged over the plurality of word addresses, temporarily storing the aligned reference pixels, and sequentially outputting the aligned and temporarily stored reference pixels. A buffer unit temporarily stores overlapping reference pixels, which are repeatedly used to generate the sub-pixels, among the reference pixels output from the bus interface unit. An interpolation unit generates first half pixels, second half pixels, first quarter pixels, and second quarter pixels, using the reference pixels output from the bus interface unit. A chroma filter unit generates chrome pixels using the reference pixels output from the bus interface unit.

Abstract: A convolution code generator according to the present invention simultaneously generates convolution codes with respect to input data word by word when a digital signal processor in which the convolution code generator can be installed has a bus configuration of a broad data width.

Abstract: An apparatus and method for verifying a logic function of a semiconductor chip in a logic chip emulation environment where a processing engine and a target interface engine interact with each other. The apparatus in accordance with the present invention generally includes a processing engine for executing a software algorithm corresponding to the logic design of the target chip, and a target interface engine interfacing with the target system for transmitting/receiving pin signals to/from the target system. The software algorithm has one or more software variables, and the transmission/reception of the pin signals by the target interface engine occurs with the execution of the software algorithm by the processing engine. The software variable and the pin signals are time-variant with the execution of the algorithm.