Patents by Inventor Chong Ming Lin
Chong Ming Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8117468Abstract: An exemplary microelectronic device is made up of two or more functional units, which are all disposed on a single chip, or die. The functional units on the die do not all need to be operational at a given time in the execution of a computer program that is controlling the microelectronic device. The present invention rapidly turns on and off the functional units of the microelectronic device as required by a program being executed. This power down can be achieved by turning off clock inputs to the functional units, interrupting the supply of power to the functional units, or deactivating input signals to the functional units. This results in a very significant reduction in power consumption and corresponding heat dissipation by the microelectronic device as compared to the conventional approach of keeping all functional units operational all of the time.Type: GrantFiled: February 19, 2009Date of Patent: February 14, 2012Inventor: Chong Ming Lin
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Patent number: 7655964Abstract: A programmable junction field effect transistor (JFET) with multiple independent gate inputs. A drain, source and a plurality of gate regions for controlling a conductive channel between the source and drain are fabricated in a semiconductor substrate. A first portion the gate regions are coupled to a first gate input and a second portion of the gate regions are coupled to a second gate input. The first and second gate inputs are electrically isolated from each other. The JFET may be programmed by applying a programming voltage to the first gate input and operated by applying a signal to the second gate input.Type: GrantFiled: March 21, 2005Date of Patent: February 2, 2010Assignee: Qspeed Semiconductor Inc.Inventors: Chong Ming Lin, Ho Yuan Yu
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Patent number: 7642832Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.Type: GrantFiled: January 22, 2008Date of Patent: January 5, 2010Assignee: Seiko Epson CorporationInventors: Ho Dai Truong, Chong Ming Lin
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Publication number: 20090228729Abstract: A microelectronic device according to the present invention is made up of two or more functional units, which are all disposed on a single chip, or die. The present invention works on the strategy that all of the functional units on the die are not, and do not need to be operational at a given time in the execution of a computer program that is controlling the microelectronic device. The present invention on a very rapid basis (typically a half clock cycle), therefore, turns on and off the functional units of the microelectronic device in accordance with the requirements of the program being executed. This power down can be achieved by one of three techniques; turning off clock inputs to the functional units, interrupting the supply of power to the functional units, or deactivating input signals to the functional units.Type: ApplicationFiled: February 19, 2009Publication date: September 10, 2009Applicant: Seiko Epson CorporationInventor: Chong Ming LIN
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Patent number: 7516436Abstract: A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.Type: GrantFiled: July 11, 2006Date of Patent: April 7, 2009Assignee: Seiko Epson CorporationInventors: Chong Ming Lin, Tatao Chuang, Tran Long, Hy Hoang
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Patent number: 7506185Abstract: A microelectronic device according to the present invention is made up of two or more functional units, which are all disposed on a single chip, or die. The present invention works on the strategy that all of the functional units on the die are not, and do not need to be operational at a given time in the execution of a computer program that is controlling the microelectronic device. The present invention on a very rapid basis (typically a half clock cycle), therefore, turns on and off the functional units of the microelectronic device in accordance with the requirements of the program being executed. This power down can be achieved by one of three techniques; turning off clock inputs to the functional units interrupting the supply of power to the functional units, or deactivating input signals to the functional units.Type: GrantFiled: June 6, 2006Date of Patent: March 17, 2009Assignee: Seiko Epson CorporationInventor: Chong Ming Lin
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Publication number: 20080129360Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.Type: ApplicationFiled: January 22, 2008Publication date: June 5, 2008Applicant: Seiko Epson CorporationInventors: Ho Dai TRUONG, Chong Ming Lin
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Patent number: 7352222Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.Type: GrantFiled: April 22, 2005Date of Patent: April 1, 2008Assignee: Seiko Epson CorporationInventors: Ho Dai Truong, Chong Ming Lin
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Patent number: 7238976Abstract: A Schottky barrier rectifier, in accordance with embodiments of the present invention, includes a first conductive layer and a semiconductor. The semiconductor includes a first doped region, a second doped region and a plurality of third doped regions. The second doped region is disposed between the first doped region and the first conductive layer. The plurality of third doped regions are disposed in the second doped region. The first doped region of the semiconductor is heavily doped with a first type of dopant (e.g., phosphorous or arsenic). The second doped region is moderately doped with the first type of dopant. The plurality of third doped regions are moderately to heavily doped with a second type of dopant.Type: GrantFiled: June 15, 2004Date of Patent: July 3, 2007Assignee: QSpeed Semiconductor Inc.Inventors: Ho-Yuan Yu, Chong-Ming Lin
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Patent number: 7227242Abstract: An etched substrate structure is augmented by conductive material to provide enhanced electrical and/or thermal performance. A semiconductor device substrate comprising active regions defined on a top surface is masked and etched to define a pattern of blind features in a bottom surface of the substrate. A conductive material is then deposited on the surface of the blind features. The replacement of semiconductor material with the conductive material lowers the resistance between the active elements on the top surface and the bottom surface. The blind features may be placed in proximity to parasitic bipolar transistors in order to increase immunity to latchup. During wafer processing, a pattern of grooves aligned opposite to a scribe street pattern may be etched on the wafer back side in order to facilitate the separation of individual devices.Type: GrantFiled: October 9, 2003Date of Patent: June 5, 2007Assignee: QSpeed Semiconductor Inc.Inventors: Chong Ming Lin, Jay Denning, Ho Yuan Yu
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Patent number: 7220661Abstract: A Schottky barrier rectifier, in accordance with embodiments of the present invention, includes a first conductive layer and a semiconductor. The semiconductor includes a first doped region, a second doped region and a plurality of third doped regions. The second doped region is disposed between the first doped region and the first conductive layer. The plurality of third doped regions are disposed in the second doped region. The first doped region of the semiconductor is heavily doped with a first type of dopant (e.g., phosphorous or arsenic). The second doped region is moderately doped with the first type of dopant. The plurality of third doped regions are moderately to heavily doped with a second type of dopant.Type: GrantFiled: December 22, 2004Date of Patent: May 22, 2007Assignee: Qspeed Semiconductor Inc.Inventors: Ho-Yuan Yu, Chong-Ming Lin
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Patent number: 7103867Abstract: A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.Type: GrantFiled: October 27, 2004Date of Patent: September 5, 2006Assignee: Seiko Epson CorporationInventors: Chong Ming Lin, Tatao Chuang, Tran Long, Hy Hoang
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Patent number: 7082543Abstract: A computer program product comprising a computer useable medium having computer program logic recorded thereon for enabling a microprocessor to compile a source code program. The computer program logic includes means for enabling the processor to receive a plurality of source code instructions, to convert each of the source code instructions into one or more machine code instructions, to generate monitoring information corresponding to each of the machine code instructions, and to enable the microprocessor to output the machine code instructions and the corresponding monitoring information. The monitoring information indicates which of a plurality of functional units of a microprocessor or a microelectronic device are to be selectively activated for executing each of the machine code instructions.Type: GrantFiled: April 30, 2003Date of Patent: July 25, 2006Assignee: Seiko Epson CorporationInventor: Chong Ming Lin
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Patent number: 7075132Abstract: A programmable junction field effect transistor (JFET) with multiple independent gate inputs. A drain, source and a plurality of gate regions for controlling a conductive channel between the source and drain are fabricated in a semiconductor substrate. A first portion the gate regions are coupled to a first gate input and a second portion of the gate regions are coupled to a second gate input. The first and second gate inputs are electrically isolated from each other. The JFET may be programmed by applying a programming voltage to the first gate input and operated by applying a signal to the second gate input.Type: GrantFiled: December 30, 2002Date of Patent: July 11, 2006Assignee: Lovoltech, Inc.Inventors: Chong Ming Lin, Ho Yuan Yu
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Patent number: 7009229Abstract: A protection device for integrated circuits. A complementary well is fabricated in a semiconductor substrate. An enhancement mode junction field effect transistor (JFET) is fabricated in the complementary well. An interface bonding pad is fabricated above the JFET. A source contact is also fabricated in the well. The gate and drain of the JFET are coupled to the interface bonding pad and the source of the JFET is coupled to the substrate.Type: GrantFiled: March 3, 2004Date of Patent: March 7, 2006Assignee: Lovoltech, IncorporatedInventors: Chong Ming Lin, Ho Yuan Yu
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Patent number: 6900682Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.Type: GrantFiled: September 25, 2003Date of Patent: May 31, 2005Assignee: Seiko Epson CorporationInventors: Ho Dai Truong, Chong Ming Lin
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Patent number: 6842885Abstract: A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.Type: GrantFiled: February 20, 2002Date of Patent: January 11, 2005Assignee: Seiko Epson CorporationInventors: Chong Ming Lin, Tatao Chuang, Tran Long, Hy Hoang
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Patent number: 6785761Abstract: A microelectronic device according to the present invention is made up of two or more functional units, which are all disposed on a single chip, or die. The present invention works on the strategy that all of the functional units on the die are not, and do not need to be operational at a given time in the execution of a computer program that is controlling the microelectronic device. The present invention on a very rapid basis (typically a half clock cycle), therefore, turns on and off the functional units of the microelectronic device in accordance with the requirements of the program being executed. This power down can be achieved by one of three techniques; turning off clock inputs to the functional units, interrupting the supply of power to the functional units, or deactivating input signals to the functional units.Type: GrantFiled: May 19, 2003Date of Patent: August 31, 2004Assignee: Seiko Epson CorporationInventor: Chong Ming Lin
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Patent number: 6774417Abstract: A protection device for integrated circuits. A complementary well is fabricated in a semiconductor substrate. An enhancement mode junction field effect transistor (JFET) is fabricated in the complementary well. An interface bonding pad is fabricated above the JFET. A source contact is also fabricated in the well. The gate and drain of the JFET are coupled to the interface bonding pad and the source of the JFET is coupled to the substrate.Type: GrantFiled: October 23, 2002Date of Patent: August 10, 2004Assignee: Lovoltech, Inc.Inventors: Chong Ming Lin, Ho Yuan Yu
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Publication number: 20040056699Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.Type: ApplicationFiled: September 25, 2003Publication date: March 25, 2004Applicant: Seiko Epson CorporationInventors: Ho Dai Truong, Chong Ming Lin