Abstract: Provided are a frequency and amplitude reduction regulation and control method and system for multi-source dynamic disturbances in deep tunnels.

Abstract: A molecular marker for identifying Vitis vinifera and its interspecific hybrid grapes and an application thereof are provided. Through whole-genome resequencing data analysis, a significant InDel locus IH1 is identified, which is located at 7,224,357 base pairs (bp) on chromosome 13 of grapes. This locus shows genotypic differences between Vitis vinifera and its interspecific hybrids. Through the differences in the number and distribution of electrophoretic bands, Vitis vinifera and its interspecific hybrids may be distinguished. Based on the characteristics of this molecular marker, it may be used for screening of interspecific hybrid progeny lines in the early stage of breeding and elimination of selfed progeny. At the same time, it may also conduct screening of the genetic background of seedlings.

Abstract: A method for breeding a new grape variety with red flesh and seedlessness based on molecular markers is provided. The molecular markers are identified significantly associated with grape red flesh and seedlessness traits through whole-genome analysis. The molecular markers may identify the phenotypic traits of grape red flesh and seedlessness at the initial stage of hybrid seedlings by using the electrophoretic banding patterns of amplified molecular marker gene fragments.

Abstract: Provided is a training method for a fault detection model, a device fault detection method and related apparatuses, relating to the field of computer technology. The method comprises: sampling a designated device based on a preset drone formation to obtain a sample sequence; performing position encoding on the sample sequence according to the drone formation to obtain a drone formation encoding result; inputting the sample sequence and the drone formation encoding result into a model to be trained to obtain a fault detection result output by the model to be trained; determining a loss value based on the fault detection result and a true value of a fault detection result of the sample sequence; and adjusting a model parameter of the model to be trained based on the loss value to obtain the fault detection model.

Abstract: This invention is forming the DMOS channel after CMOS active layer before gate poly layer to make the modular DMOS process step easily adding into the sub-micron CMOS or BiCMOS process. And DMOS source is formed by implant which is separated by a spacer self-aligned to the window for DMOS body. By this method, the performance of CMOS and bipolar devices formed original CMOS or BiCMOS process keeps no change. The product design kit, such as standard cell library of CMOS and BiCMOS, can be used continuously with no change.

Abstract: A lateral DMOS structure includes a light doped p-type region beneath and near the gate at the drain side. The electric field on the surface near the gate is reduced. Thus the electric field near the gate decreases, and the SOA (safe operating area) of the lateral DMOS device increases and long time reliability improves. Moreover, the lateral DMOS of the invention can be fabricated without increasing the manufacturing cost.

Abstract: The present invention relates to a lateral PNP transistor and the method of manufacturing the same. The medium doping N-type base area and the light doping P? collector area were first introduced in the structure before the formation of P+ doping emitter area and the collector area. The emitter-base-collector doping profile in the lateral and the base width of LPNP were similar to NPN. The designer can optimize the doping profile and area size of each area according to the request of the current gain (Hfe), collector-base breakdown voltage (BVceo), and early voltage (VA) of LPNP transistor. These advantages may cause to reduce the area and enhance performance of the LPNP transistor.

Abstract: A lateral DMOS structure includes a light doped p-type region beneath and near the gate at the drain side. The electric field on the surface near the gate is reduced. Thus the electric field near the gate decreases, and the SOA (safe operating area) of the lateral DMOS device increases and long time reliability improves. Moreover, the lateral DMOS of the invention can be fabricated without increasing the manufacturing cost.

Abstract: This invention is forming the DMOS channel after CMOS active layer before gate poly layer to make the modular DMOS process step easily adding into the sub-micron CMOS or BiCMOS process. And DMOS source is formed by implant which is separated by a spacer self-aligned to the window for DMOS body. By this method, the performance of CMOS and bipolar devices formed original CMOS or BiCMOS process keeps no change. The product design kit, such as standard cell library of CMOS and BiCMOS, can be used continuously with no change.

Abstract: The present invention discloses a high voltage and high frequency poly emitter bipolar structure with improved breakdown voltage performance. The advantage of the poly emitter bipolar structures is that the SOD coating layer can improve the breakdown voltage of a capacitor structure higher to be 6-8 volts. In addition, the poly emitter bipolar structure having the inter-level dielectric layer deposited by PECVD on the emitter and collector by optimizing PECVD deposition process condition to adjust the charge in the oxide of inter-level dielectric layer has a breakdown voltage higher than 30 volts.

Abstract: The present invention discloses a method for fabricating bipolar integrated circuits, wherein LOCOS technology is used to define the active regions needed by all elements so that the self-alignment of the associated layers can be realized, and implant resistor regions are also directly defined in the active regions by local oxide layers; after base regions have been driven in the wafer, the resistors are implanted into the wafer so that the cost of resistor photomasks can be saved; silicon nitride is adopted to be the material of the dielectric layers of the capacitors, and with the characteristic of a buffering oxide etchant that etches oxide faster than it etches silicon nitride, the conventional deposition sequence of the dielectric layer is changed so that the formation of the dielectric layer needs only a single photomask.

Abstract: A fabrication method is applied to the bipolar integrated circuit, which combines with various patterns of the masks using in the different processes to form a combination mask. By using the combination mask, a silicon dioxide layer is etched to produce the open windows required in the different processes. Thereafter, according to the requirements of different processes, the unused windows are covered with photoresists to avoid the alignment errors resulted from the pattering and etching of different masks. Because the method doesn't need to reserve tolerance for alignment errors, the degree of integration of the semiconductor processes is enhanced and the cost of production is reduced.

Abstract: The present invention relates to a lateral PNP transistor and the method of manufacturing the same. The medium doping N-type base area and the light doping P? collector area were first introduced in the structure before the formation of P+ doping emitter area and the collector area. The emitter-base-collector doping profile in the lateral and the base width of LPNP were similar to NPN. The designer can optimize the doping profile and area size of each area according to the request of the current gain (Hfe), collector-base breakdown voltage (BVceo), and early voltage (VA) of LPNP transistor. These advantages may cause to reduce the area and enhance performance of the LPNP transistor.

Abstract: The present invention relates to a lateral PNP transistor and the method of manufacturing the same. The medium doping N-type base area and the light doping P? collector area were first introduced in the structure before the formation of P+ doping emitter area and the collector area. The emitter-base-collector doping profile in the lateral and the base width of LPNP were similar to NPN. The designer can optimize the doping profile and area size of each area according to the request of the current gain (Hfe), collector-base breakdown voltage (BVceo), and Early voltage (VA) of LPNP transistor. These advantages may cause to reduce the area and enhance performance of the LPNP transistor.

Abstract: A bimetal layer manufacturing method includes the procedure of: forming a first dielectric layer on the surface of a semiconductor substrate which has a first metal layer (conductive layer) of a selected pattern formed thereon; forming a SOG layer on the surface of the first dielectric layer; forming a second dielectric layer; forming required via holes on the foregoing layers until reaching the first metal layer; forming a linear layer from a dielectrics material through PECVD; removing unnecessary linear layer from selected locations through an anisotropic plasma etching process; finally forming a second metal layer on a selected surface of the linear layer where MIM capacitors to be formed, and forming connection plugs in the via openings without generating via hole poison.