Patents by Inventor Chong Soon Lim

Chong Soon Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250119573
    Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry corrects a base motion vector using a correction value in a fixed direction; and encodes a current partition by using the corrected base motion vector corrected. The correction value is specified by an index indicating one of correction values included in a table. The table is selected from among a plurality of tables, wherein the correction values in one of the plurality of tables have different increments from the correction values in another one of the plurality of tables.
    Type: Application
    Filed: November 18, 2024
    Publication date: April 10, 2025
    Inventors: Jing Ya LI, Chong Soon LIM, Sughosh Pavan SHASHIDHAR, Ru Ling LIAO, Hai Wei SUN, Han Boon TEO, Kiyofumi ABE, Tadamasa TOMA, Takahiro NISHI
  • Patent number: 12273522
    Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation, determines whether a first block is available and whether a second block is available, the first block and the second block being defined relative to a current block to be processed; selects a context model based on whether the first block is available, whether the second block is available, which of inter prediction and intra prediction is to be applied to the first block, and which of inter prediction and intra prediction is to be applied to the second block; and encodes, using the context model selected, a parameter indicating which of intra prediction and inter prediction is to be applied to the current block.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: April 8, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Chong Soon Lim, Hai Wei Sun, Jing Ya Li, Han Boon Teo, Ru Ling Liao, Che Wei Kuo, Tadamasa Toma, Takahiro Nishi, Kiyofumi Abe
  • Publication number: 20250113051
    Abstract: An encoder which includes circuitry and memory. Using the memory, the circuitry generates a list which includes candidates for a first motion vector for a first partition. The list has a maximum list size and an order of the candidates, and at least one of the maximum list size or the order of the candidates is dependent on at least one of a partition size or a partition shape of the first partition. The circuitry selects the first motion vector from the candidates included in the list; encodes an index indicating the first motion vector among the candidates in the list into the bitstream based on the maximum list size; and generates the predicted image for the first partition using the first motion vector.
    Type: Application
    Filed: December 13, 2024
    Publication date: April 3, 2025
    Inventors: Chong Soon LIM, Hai Wei SUN, Sughosh Pavan SHASHIDHAR, Han Boon TEO, Ru Ling LIAO, Jing Ya LI, Tadamasa TOMA, Takahiro NISHI, Kiyofumi ABE, Ryuichi KANOH
  • Publication number: 20250106423
    Abstract: An image encoder includes circuitry and a memory, wherein the circuitry, in operation, obtains a current block from a coding tree unit (CTU); determines whether inter prediction is to be applied to the current block; in response to determining that the inter prediction is to be applied, performs a partition prediction process; and, in response to determining that the inter prediction is not to be applied, encodes the current block without using the partition prediction process. The partition prediction process includes predicting first values of a set of pixels between a first partition and a second partition in the current block, using a first motion vector for the first partition; predicting second values of the set of pixels, using a second motion vector for the second partition; weighting the first values and the second values; and generating a prediction image for the current block using the weighted first and second values.
    Type: Application
    Filed: December 6, 2024
    Publication date: March 27, 2025
    Inventors: Kiyofumi ABE, Takahiro NISHI, Tadamasa TOMA, Ryuichi KANOH, Chong Soon LIM, Ru Ling LIAO, Hai Wei SUN, Sughosh Pavan SHASHIDHAR, Han Boon TEO, Jing Ya LI
  • Publication number: 20250106440
    Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry determines whether to split a current luma virtual pipeline decoding unit (VPDU) into smaller blocks. When it is determined not to split the current luma VPDU into smaller blocks, the circuitry predicts a block of chroma samples without using luma samples. When it is determined to split the luma VPDU into smaller blocks, the circuitry predicts the block of chroma samples using luma samples. The circuitry encodes the block using the predicted chroma samples.
    Type: Application
    Filed: December 6, 2024
    Publication date: March 27, 2025
    Inventors: Chong Soon LIM, Hai Wei SUN, Han Boon TEO, Jing Ya LI, Che-Wei KUO, Tadamasa TOMA, Takahiro NISHI, Kiyofumi ABE, Yusuke KATO
  • Publication number: 20250106424
    Abstract: An image encoder writes a first parameter and a second parameter to a bitstream, and derives a partition mode based on the first and second parameters. Responsive to the derived partition mode being a first partition mode, the image encoder executes the first partition mode including: splitting a block of a picture into a plurality of first blocks including a N×2N block sized N pixels by 2N pixels; splitting the N×2N block, wherein a ternary split is allowed to split the N×2N block in a vertical direction, which is a direction along the 2N pixels, into a plurality of sub blocks including at least one sub block sized N/4×2N, while a binary split is not allowed to split the N×2N block in the vertical direction into two sub blocks that are equally sized N/2×2N; and encoding the plurality of sub blocks.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Inventors: Chong Soon LIM, Hai Wei SUN, Sughosh Pavan SHASHIDHAR, Ru Ling LIAO, Han Boon TEO, Takahiro NISHI, Ryuichi KANOH, Tadamasa TOMA
  • Publication number: 20250106417
    Abstract: A decoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: decodes a plurality of sets of neural network information each of which identifies a neural network filter; decodes, from one access unit, two or more sets of activation information each of which specifies one set of neural network information among the plurality of sets of neural network information; and applies, to one picture, two or more neural network filters identified by two or more sets of neural network information specified by the two or more sets of activation information.
    Type: Application
    Filed: December 11, 2024
    Publication date: March 27, 2025
    Inventors: Han Boon TEO, Jingying GAO, Chong Soon LIM, Praveen Kumar YADAV, Kiyofumi ABE, Takahiro NISHI, Tadamasa TOMA
  • Patent number: 12262049
    Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry, in operation, selects an encoding mode from among candidates including a decoder-side motion vector refinement (DMVR) encoding mode and a partition encoding mode. When the DMVR encoding mode is selected, the circuitry: obtains a first motion vector for a first image block; derives a second motion vector from the first motion vector using motion search; and generates a prediction image for the first image block using the second motion vector. When the partition encoding mode is selected, the circuitry: determines a plurality of partitions in a second image block; obtains a third motion vector for each partition; and generates a prediction image for the second image block using the third motion vector, without deriving a fourth motion vector from the third motion vector using motion search.
    Type: Grant
    Filed: December 19, 2023
    Date of Patent: March 25, 2025
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma, Ryuichi Kanoh, Chong Soon Lim, Ru Ling Liao, Hai Wei Sun, Sughosh Pavan Shashidhar, Han Boon Teo, Jing Ya Li
  • Patent number: 12262010
    Abstract: An encoder according to one aspect of the present disclosure encodes a block of an image, and includes a processor and memory connected to the processor. Using the memory, the processor partitions a block into a plurality of sub blocks and encodes a sub block included in the plurality of sub blocks in an encoding process including at least a transform process or a prediction process. The block is partitioned using a multiple partition including at least three odd-numbered child nodes and each of a width and a height of each of the plurality of sub blocks is a power of two.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: March 25, 2025
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Chong Soon Lim, Hai Wei Sun, Sughosh Pavan Shashidhar, Han Boon Teo, Ru Ling Liao, Takahiro Nishi, Tadamasa Toma
  • Patent number: 12262004
    Abstract: An encoder includes circuitry which generates a first coefficient value by applying a CCALF process to a first reconstructed image sample of a luma component; generates a second coefficient value by applying an ALF process to a second reconstructed image sample of a chroma component; generates a third coefficient value by adding the first coefficient value to the second coefficient value; and encodes a third reconstructed image sample of the chroma component using the third coefficient value. The circuitry writes a first parameter into a sequence parameter set; writes a second parameter into a parameter set of a picture in response to a value of the first parameter being 1; writes a third parameter into a slice header in response to the value of the first parameter being 1; and writes a fourth parameter into a coding tree unit in response to a value of the third parameter being 1.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: March 25, 2025
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Che-Wei Kuo, Chong Soon Lim, Jing Ya Li, Han Boon Teo, Hai Wei Sun, Chu Tong Wang, Tadamasa Toma, Takahiro Nishi, Kiyofumi Abe, Yusuke Kato
  • Patent number: 12262038
    Abstract: A decoder includes circuitry which, in operation, parses a first flag indicating whether a CCALF (cross component adaptive loop filtering) process is enabled for a first block located adjacent to a left side of a current block; parses a second flag indicating whether the CCALF process is enabled for a second block located adjacent to an upper side of the current block; determines a first index associated with a color component of the current block; and derives a second index indicating a context model, using the first flag, the second flag, and the first index. The circuitry, in operation, performs entropy decoding of a third flag indicating whether the CCALF process is enabled for the current block, using the context model indicated by the second index; and performs the CCALF process on the current block in response to the third flag indicating the CCALF process is enabled for the current block.
    Type: Grant
    Filed: January 22, 2024
    Date of Patent: March 25, 2025
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Che-Wei Kuo, Chong Soon Lim, Han Boon Teo, Jing Ya Li, Hai Wei Sun, Chu Tong Wang, Tadamasa Toma, Takahiro Nishi, Kiyofumi Abe, Yusuke Kato
  • Publication number: 20250097475
    Abstract: An image encoder includes circuitry, and a memory connected to the circuitry. The circuitry, in operation, determines a first region and a second region in an input image, generates a first image from the input image by applying a first prefilter to the first region and a second prefilter to the second region, determines a first parameter relating to the first region and a second parameter relating to the second region, and generates a bitstream by encoding the first region based on the first parameter, encoding the second region based on the second parameter, encoding the first prefilter or a first postfilter corresponding to the first prefilter, and encoding the second prefilter or a second postfilter corresponding to the second prefilter.
    Type: Application
    Filed: December 4, 2024
    Publication date: March 20, 2025
    Inventors: Jingying GAO, Han Boon Teo, Chong Soon Lim, Praveen Kumar Yadav, Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma
  • Publication number: 20250095214
    Abstract: An encoding device includes: memory; and a circuit. In operation, the circuit: when a first triangle satisfies a condition, performs a first process including a process of using the first triangle to derive a predicted value of a current vertex to be encoded of a second triangle; when the first triangle does not satisfy the condition, performs a second process including a process of using a third triangle different from the first triangle and the second triangle to derive the predicted value of the current vertex; and encodes the current vertex using the predicted value.
    Type: Application
    Filed: December 2, 2024
    Publication date: March 20, 2025
    Inventors: Toshiyasu SUGIO, Noritaka IGUCHI, Takahiro NISHI, Chong Soon LIM, Zheng WU, Han Boon TEO, Keng Liang LOI, Chung Dean HAN, Georges NADER, Farman DUMANOV
  • Publication number: 20250097476
    Abstract: A decoder includes memory and a processor coupled to the memory and configured to: generate a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component; clip the first coefficient value such that the clipped first coefficient value is within a first range from ?27 to 27?1; generate a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component; clip the second coefficient value such that the clipped second coefficient value is within a second range different from the first range; generate a third coefficient value by adding the clipped first coefficient value to the clipped second coefficient value; and generate a third reconstructed image sample of the chroma component using the third coefficient value.
    Type: Application
    Filed: November 25, 2024
    Publication date: March 20, 2025
    Inventors: Jing Ya LI, Han Boon TEO, Chong Soon LIM, Hai Wei SUN, Che-Wei KUO, Chu Tong WANG, Tadamasa TOMA, Takahiro NISHI, Kiyofumi ABE, Yusuke KATO
  • Publication number: 20250097452
    Abstract: An encoder includes: circuitry; and memory coupled to the circuitry. In operation, the circuitry: derives a base motion vector to be used in predicting a current block to be encoded; derives a first motion vector different from the base motion vector; derives a motion vector difference based on a difference between the base motion vector and the first motion vector; determines whether the motion vector difference is greater than a threshold; modifies the first motion vector when the motion vector difference is determined to be greater than the threshold, and does not modify the first motion vector when the motion vector difference is determined not to be greater than the threshold; and encodes the current block using the first motion vector modified or the first motion vector not modified.
    Type: Application
    Filed: December 5, 2024
    Publication date: March 20, 2025
    Inventors: Jing Ya LI, Chong Soon LIM, Ru Ling LIAO, Hai Wei Sun, Han Boon TEO, Kiyofumo ABE, Tadamss Toma, Takahiro NISHI
  • Publication number: 20250097477
    Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation, generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component, and generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component. The circuitry modifies the first coefficient value by performing an arithmetic right shift by 7 bits on the first coefficient value. The circuitry generates a third coefficient value by adding the modified first coefficient value to the second coefficient value, and encodes a third reconstructed image sample of the chroma component using the third coefficient value.
    Type: Application
    Filed: December 5, 2024
    Publication date: March 20, 2025
    Inventors: Jing Ya LI, Chong Soon LIM, Han Boon TEO, Hai Wei SUN, Che-Wei KUO, Chu Tong WANG, Tadamasa TOMA, Takahiro NISHI, Kiyofumi ABE, Yusuke KATO
  • Publication number: 20250088654
    Abstract: An image coding method includes: selecting a first picture from plural pictures; setting a first temporal motion vector prediction flag which is associated with the first picture and is a temporal motion vector prediction flag indicating whether or not temporal motion vector prediction is to be used, to indicate that the temporal motion vector prediction is not to be used, and coding the first temporal motion vector prediction flag; coding the first picture without using the temporal motion vector prediction; and coding a second picture which follows the first picture in coding order, with referring to a motion vector of a picture preceding the first picture in coding order being prohibited.
    Type: Application
    Filed: November 22, 2024
    Publication date: March 13, 2025
    Inventors: Sue Mon Thet NAING, Chong Soon Lim, Kyaw Kyaw Win, Hai Wei Sun, Viktor Wahadaniah, Takahiro Nishi, Hisao Sasai, Youji Shibahara, Toshiyasu Sugio, Kyoko Tanikawa, Toru Matsunobu, Kengo Terada
  • Patent number: 12250384
    Abstract: An encoder includes circuitry and memory connected to the circuitry. The circuitry: derives an absolute value of a sum of gradient values in first and second ranges; derives, as a first parameter, a total sum of absolute values of sums of gradient values derived respectively for pairs of relative pixel positions; derives a pixel difference value between pixel values in the first and second ranges; inverts or maintains a plus or minus sign of the pixel difference value, according to a plus or minus sign of the sum of the gradient values indicating the sum of the gradient values in the first and second ranges; derives, as a second parameter, a total sum of pixel difference values each having the plus or minus sign inverted or maintained, the pixel difference values derived respectively for the relative pixel positions; and generates a prediction image using the first and second parameters.
    Type: Grant
    Filed: August 16, 2023
    Date of Patent: March 11, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Jing Ya Li, Ru Ling Liao, Chong Soon Lim, Han Boon Teo, Hai Wei Sun, Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma
  • Publication number: 20250071272
    Abstract: An image decoding device includes circuitry and a memory connected to the circuitry, in which in operation, the circuitry acquires a first image and a plurality of first filter sets by decoding a bitstream, generates and outputs a second image by selecting one first filter set from the plurality of first filter sets based on usage information indicating an image usage, and applying the first filter set having been selected to the first image.
    Type: Application
    Filed: November 13, 2024
    Publication date: February 27, 2025
    Inventors: Jingying GAO, Han Boon TEO, Chong Soon LIM, Praveen Kumar YADAV, Kiyofumi ABE, Takahiro NISHI, Tadamasa TOMA
  • Publication number: 20250071275
    Abstract: An encoder includes circuitry and a memory coupled to the circuitry. The circuitry, in operation, determines whether or not a ternary split process of splitting a block into three sub blocks in a first direction parallel to a first longer side of the block is allowed by comparing a size of a second shorter side of the block to a minimum threshold value. The circuitry, responsive to the ternary split process being allowed, writes, into a bitstream, a split direction parameter indicative of a splitting direction. The circuitry, in operation, splits the block into a plurality of sub blocks in a direction indicated by the split direction parameter; and encodes the plurality of sub blocks. The minimum threshold value corresponds to a minimum size supported in a transform process.
    Type: Application
    Filed: November 14, 2024
    Publication date: February 27, 2025
    Inventors: Sughosh Pavan SHASHIDHAR, Hai Wei SUN, Chong Soon LIM, Ru Ling LIAO, Han Boon TEO, Jing Ya LI, Takahiro NISHI, Kiyofumi ABE, Ryuichi KANOH, Tadamasa TOMA