Patents by Inventor Chong Un Tan
Chong Un Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230411340Abstract: A semiconductor device includes a signal carrier medium such as a PCB substrate having first and second opposed surfaces and a cavity formed in the second surface. A first set of one or more semiconductor dies are mounted on the first surface, and a second set of one or more semiconductor dies are mounted within the cavity. The first and/or second sets of semiconductor dies may be memory dies.Type: ApplicationFiled: May 17, 2022Publication date: December 21, 2023Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Lee Kong Yu, Yoong Tatt Chin, Kim Lee Bock, Paramjeet Gill, Wei Chiat Teng, Chong Un Tan
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Patent number: 11798918Abstract: A semiconductor device package includes an embedded plurality of solder balls within an integrated circuit die (ICD) substrate In one embodiment, the integrated circuit die (ICD) substrate has a top surface and a bottom surface, and a plurality of solder balls at least partially embedded in the ICD substrate, where each of the plurality of solder balls comprises an exposed surface that is substantially flat and parallel planar to the bottom surface, and where the exposed surface of each of the plurality of solder balls is disposed in the bottom surface. In certain examples, the apparatuses also include a plurality of integrated circuit dies stacked on the top surface of the ICD substrate.Type: GrantFiled: November 30, 2021Date of Patent: October 24, 2023Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Muhammad Bashir Mansor, Chong Un Tan, Shivaram Sahadevan, Mickaldass Santanasamy, Muhammad Faizul Mohd Yunus, Chin Koon Tang
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Patent number: 11699685Abstract: A semiconductor assembly includes a first die and a second die. The semiconductor assembly also includes a film on die (FOD) layer configured to attach the first die to the second die. The FOD layer is disposed on a first surface of the first die. The FOD layer includes a first portion comprising a first die attach film (DAF) disposed on an inner region of the first surface. The FOD layer also includes a second portion that includes a second DAF disposed on a peripheral region of the first surface surrounding the inner region. The second DAF includes a different material than the first DAF.Type: GrantFiled: July 14, 2021Date of Patent: July 11, 2023Assignee: Western Digital Technologies, Inc.Inventors: Ling Yang, Hui Xu, Chong Un Tan
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Publication number: 20230137512Abstract: A semiconductor memory device, also referred to as a solid state drive, includes thermally conductive components such as a conductive coating to draw heat away from the semiconductive package. The coating may also be electrically conductive to provide shielding from and absorption of electromagnetic interference. In examples, a semiconductor device including a substrate may be affixed to an edge connector printed circuit board with solder balls to form a solid state drive. In further examples, the substrate may be omitted, and semiconductor memory dies, a controller die and other electronic components may be directly surface mounted to an edge connector printed circuit board to form a solid state drive.Type: ApplicationFiled: November 3, 2021Publication date: May 4, 2023Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Hui Xu, Kim Lee Bock, Rama Shukla, Chong Un Tan, Yoong Tatt Chin, Shrikar Bhagath
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Publication number: 20230020021Abstract: A semiconductor assembly includes a first die and a second die. The semiconductor assembly also includes a film on die (FOD) layer configured to attach the first die to the second die. The FOD layer is disposed on a first surface of the first die. The FOD layer includes a first portion comprising a first die attach film (DAF) disposed on an inner region of the first surface. The FOD layer also includes a second portion that includes a second DAF disposed on a peripheral region of the first surface surrounding the inner region. The second DAF includes a different material than the first DAF.Type: ApplicationFiled: July 14, 2021Publication date: January 19, 2023Applicant: Western Digital Technologies, Inc.Inventors: Ling Yang, Hui Xu, Chong Un Tan
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Publication number: 20220093570Abstract: A semiconductor device package includes an embedded plurality of solder balls within an integrated circuit die (ICD) substrate In one embodiment, the integrated circuit die (ICD) substrate has a top surface and a bottom surface, and a plurality of solder balls at least partially embedded in the ICD substrate, where each of the plurality of solder balls comprises an exposed surface that is substantially flat and parallel planar to the bottom surface, and where the exposed surface of each of the plurality of solder balls is disposed in the bottom surface. In certain examples, the apparatuses also include a plurality of integrated circuit dies stacked on the top surface of the ICD substrate.Type: ApplicationFiled: November 30, 2021Publication date: March 24, 2022Applicant: Western Digital Technologies, Inc.Inventors: MUHAMMAD BASHIR MANSOR, CHONG UN TAN, SHIVARAM SAHADEVAN, MICKALDASS SANTANASAMY, MUHAMMAD FAIZUL MOHD YUNUS, CHIN KOON TANG
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Publication number: 20210384114Abstract: A semiconductor device package includes an embedded plurality of solder balls within an integrated circuit die (ICD) substrate In one embodiment, the integrated circuit die (ICD) substrate has a top surface and a bottom surface, and a plurality of solder balls at least partially embedded in the ICD substrate, where each of the plurality of solder balls comprises an exposed surface that is substantially flat and parallel planar to the bottom surface, and where the exposed surface of each of the plurality of solder balls is disposed in the bottom surface. In certain examples, the apparatuses also include a plurality of integrated circuit dies stacked on the top surface of the ICD substrate.Type: ApplicationFiled: June 4, 2020Publication date: December 9, 2021Applicant: Western Digital Technologies, Inc.Inventors: MUHAMMAD BASHIR MANSOR, CHONG UN TAN, SHIVARAM SAHADEVAN, MICKALDASS SANTANASAMY, MUHAMMAD FAIZUL MOHD YUNUS, CHIN KOON TANG
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Patent number: 11195786Abstract: A semiconductor device package includes an embedded plurality of solder balls within an integrated circuit die (ICD) substrate In one embodiment, the integrated circuit die (ICD) substrate has a top surface and a bottom surface, and a plurality of solder balls at least partially embedded in the ICD substrate, where each of the plurality of solder balls comprises an exposed surface that is substantially flat and parallel planar to the bottom surface, and where the exposed surface of each of the plurality of solder balls is disposed in the bottom surface. In certain examples, the apparatuses also include a plurality of integrated circuit dies stacked on the top surface of the ICD substrate.Type: GrantFiled: June 4, 2020Date of Patent: December 7, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Muhammad Bashir Mansor, Chong Un Tan, Shivaram Sahadevan, Mickaldass Santanasamy, Muhammad Faizul Mohd Yunus, Chin Koon Tang
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Patent number: 10418334Abstract: A semiconductor die is disclosed including corner recesses to prevent cracking of the semiconductor die during fabrication. Prior to dicing the semiconductor die from the wafer, recesses may be formed in the wafer at corners between any pair of semiconductor die. The recesses may be formed by a laser or photolithographic processes in the kerf area between semiconductor die. Once formed, the corner recesses prevent cracking and damage to semiconductor die which could otherwise occur at the corners of adjacent semiconductor die as the adjacent semiconductor die move relative to each other during the backgrind process.Type: GrantFiled: June 22, 2017Date of Patent: September 17, 2019Assignee: SanDisk Semiconductor (Shanghai) Co. Ltd.Inventors: Hang Zhang, Weili Wang, Junrong Yan, Kim Lee Bock, Chee Keong Chin, Chong Un Tan, Xin Tian
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Patent number: 10276546Abstract: A semiconductor device with die tilt control is disclosed. In one embodiment, a semiconductor device is provided comprising: a substrate; a first semiconductor die stacked on the substrate; and a plurality of additional semiconductor dies stacked on the first semiconductor die, wherein the plurality of additional semiconductor dies are stacked in an offset configuration, such that an edge of each of the plurality of additional semiconductor dies overhangs an edge of the semiconductor die on which it is stacked; wherein a thickness of a top-most semiconductor die of the plurality of additional semiconductor dies is greater than a thickness of any of the other additional semiconductor dies. Other embodiments are provided.Type: GrantFiled: May 2, 2018Date of Patent: April 30, 2019Assignee: SanDisk Semiconductor (Shanghai) Co. Ltd.Inventors: Shuai Wu, Xu Wang, Seanan Wang, Peng Lu, Li Wang, Chong Un Tan
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Patent number: 10128218Abstract: A semiconductor device is disclosed that is formed with die bond pads at an edge of the semiconductor die. The die bond pads may be formed partially in a kerf area between semiconductor die on a wafer. When the wafer is diced, the die bond pads are severed along their length, leaving a portion of the die bond pads exposed at an edge of the diced semiconductor die. Having die bond pads at the edge of the die minimizes the offset between die when stacked into a package.Type: GrantFiled: June 22, 2017Date of Patent: November 13, 2018Assignee: SanDisk Semiconductor (Shanghai) Co. Ltd.Inventors: Junrong Yan, Chee Keong Chin, Chong Un Tan, Ming Xia Wu, Kim Lee Bock, Shrikar Bhagath
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Publication number: 20180174983Abstract: A semiconductor die is disclosed including corner recesses to prevent cracking of the semiconductor die during fabrication. Prior to dicing the semiconductor die from the wafer, recesses may be formed in the wafer at corners between any pair of semiconductor die. The recesses may be formed by a laser or photolithographic processes in the kerf area between semiconductor die. Once formed, the corner recesses prevent cracking and damage to semiconductor die which could otherwise occur at the corners of adjacent semiconductor die as the adjacent semiconductor die move relative to each other during the backgrind process.Type: ApplicationFiled: June 22, 2017Publication date: June 21, 2018Applicant: SANDISK SEMICONDUCTOR (SHANGHAI) CO., LTD.Inventors: Hang Zhang, Weili Wang, Junrong Yan, Kim Lee Bock, Chee Keong Chin, Chong Un Tan, Xin Tian
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Publication number: 20180175006Abstract: A semiconductor device is disclosed that is formed with die bond pads at an edge of the semiconductor die. The die bond pads may be formed partially in a kerf area between semiconductor die on a wafer. When the wafer is diced, the die bond pads are severed along their length, leaving a portion of the die bond pads exposed at an edge of the diced semiconductor die. Having die bond pads at the edge of the die minimizes the offset between die when stacked into a package.Type: ApplicationFiled: June 22, 2017Publication date: June 21, 2018Applicant: SANDISK SEMICONDUCTOR (SHANGHAI) CO., LTD.Inventors: Junrong Yan, Chee Keong Chin, Chong Un Tan, Ming Xia Wu, Kim Lee Bock, Shrikar Bhagath
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Patent number: 6864423Abstract: A lead frame with a plurality of bump terminals is provided. Stamping an indentation into each lead in the lead frame forms the bump terminals. The bump terminals will be used as contact points in a completed semiconductor device.Type: GrantFiled: December 15, 2000Date of Patent: March 8, 2005Assignee: Semiconductor Component Industries, L.L.C.Inventors: Aik Chong Tan, Chong Un Tan, Chee Chuan Chew
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Publication number: 20020074147Abstract: A lead frame with a plurality of bump terminals is provided. Stamping an indentation into each lead in the lead frame forms the bump terminals. The bump terminals will be used as contact points in a completed semiconductor device.Type: ApplicationFiled: December 15, 2000Publication date: June 20, 2002Applicant: Semiconductor Components Industries, LLCInventors: Aik Chong Tan, Chong Un Tan, Chee Chuan Chew