Abstract: A communication apparatus comprises a radio transceiver and a modem processor. The radio transceiver is configured to transmit or receive signals. The modem processor is coupled to the radio transceiver and configured to perform operations comprising: performing a beam management, to train a first receiver (Rx) beam; receiving a physical downlink shared channel (PDSCH) according to the first Rx beam; selecting at least one second Rx beam according to a scenario, if a first performance indicator of the first Rx beam is lower than a previous first performance indicator of the first Rx beam by a first threshold; determining at least one second performance indicator of the PDSCH according to a round-robin test; selecting a third Rx beam from the at least one second Rx beam according to the at least one second performance indicator; and receiving the PDSCH according to the third Rx beam.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a device. The device applies Nso sensing beam vectors to Nso received signals at Nant antennas to obtain Nso measurements, respectively, Nso and Nant each being an integer greater than or equal to 1. The device determines a beam vector based on the Nso measurements and the Nso sensing beam vectors.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The UE receives, from a base station, a configuration specifying an initial aggregated bandwidth W0 carried on C0 component carriers on which a reception unit (RXU) of the UE is to receive signals. The UE determines a total bandwidth WTOT on which the UE is capable of receiving signals. The UE determines, based on WTOT and W0, an initial hardware limit of Q0? RXUs that the UE is allowed to activate concurrently. The UE determines an adjusted aggregated bandwidth W1 carried on C1 component carriers on which an RXU of the UE is to receive signals based on a channel condition between the UE and the base station.

Abstract: A method of cross component carrier (Cross-CC) beam management is proposed. A transceiver uses multiple CCs' channel measurements to obtain a beam vector such that better performance can be achieved by utilizing wideband channel. The transceiver derives the beam vector by using the channel measurements of a set of selected CCs applied with a carrier weight factor. The transceiver utilizes beam management reference signal (BM-RS) of the set of selected CCs to derive the beam vector, e.g., an optimal beam. In one embodiment, the carrier weight factor can be the number of BM-RS REs of each CC. In another embodiment, the channel measurements can be SNR/RSRP, and the carrier weight factor can be the SNR/RSRP of each CC.

Abstract: A method to jointly perform beam management, synchronization, and L1 measurements using a single synchronization signal block (SSB) burst in NR systems is proposed to improve data rate and to reduce power consumption. In a scheduling based SSB method, a UE is scheduled to perform either beam management or synchronization and L1 measurements alternatively. In a joint SSB method, a UE performs beam management, synchronization, and L1 RSRP/SNR measurements within a single SSB burst simultaneously. The UE can dynamically switch between the two SSB methods based on predefined conditions. Further, multiple joint SSB modes are introduced for the joint SSB method, where either 3 OFDM symbols or 4 OFDM symbols of each SSB burst are used. UE can dynamically switch among the joint SSB modes depending on contamination level on the OFDM symbol carrying PSS.

Abstract: The invention provides a method for antenna selectin of a user equipment (UE). The UE may comprise a plurality of antennas. The method may comprise calculating one or more quality evaluations respectively associated with one or more first antenna subsets, and selecting one of the one or more first antenna subsets according to the one or more quality evaluations. Each antenna subset may include one or more of the plurality of antennas. Each quality evaluation may be calculated under a condition that the antenna(s) included in the associated antenna subset is (are) used to communicate.

Abstract: Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.

Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.

Abstract: Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer. Alternatively or additionally, the processor may generate the QC-LDPC code including a base matrix a portion of which forming a kernel matrix that corresponds to a code rate of at least a threshold value.

Abstract: Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.

Abstract: An apparatus determines a code block size (CBS) of information bits contained in a codeword of low-density parity check (LDPC) coding. The apparatus compares the CBS with at least one threshold, determines, based on a result of the comparison, a Kb number and determines a Kp number based on a code rate and the Kb number. The apparatus generates a parity check matrix. An information portion of the parity check matrix is a first matrix formed by M number of second square matrices. M is equal to Kp multiplied by Kb. A total number of columns in the Kb number of second square matrices is equal to a total number of bits of the CBS. One or more matrices of the M number of second square matrices are circular permutation matrices. The apparatus operates an LDPC encoder or an LDPC decoder based on the parity check matrix.

Abstract: Concepts and schemes pertaining to structure of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide encoded data. A transceiver of the apparatus transmits the encoded data to at least one network node of a wireless network. In encoding the data to provide the encoded data, the processor encodes the data to result in each code block in the encoded data comprising a respective bit-level interleaver.

Abstract: Aspects of the disclosure provide an apparatus and a method for error correction based on a matrix. The apparatus includes memory and processing circuitry. The memory is configured to store the matrix associated with a set of parity bits. The matrix having rows and columns includes elements having values corresponding to either a first state or a second state. The matrix also includes a row having two elements with values corresponding to the first state. One of the two elements is a parity element corresponding to a parity bit associated with the row. Further, other elements in a same column as the parity element have values corresponding to the second state. The processing circuitry is configured to implement error correction based on the matrix. In another embodiment, the processing circuitry is configured to encode a data unit by generating the set of parity bits from the data unit based on the matrix and to form a codeword that includes the data unit and the set of parity bits.

Abstract: Aspects of the disclosure provide an apparatus that includes transmitting circuit and processing circuit. The transmitting circuitry is configured to transmit wireless signals. The processing circuitry is configured to encode a set of information bits with a code that is configured for incremental redundancy to generate a code word that includes the information bits and parity bits, buffer the code word in a circular buffer, determine a start position in the circular buffer based on a redundancy version that is selected from a plurality of redundancy versions based on a scenario evaluation of a previous transmission associated with the set of information bits, and transmit, via the transmitting circuitry, a selected portion of the code word from the start position.

Abstract: Concepts and schemes pertaining to shift coefficient and lifting factor design for NR LDPC code are described. A processor of an apparatus may generate a quasi-cyclic-low-density parity-check (QC-LDPC) code and encode data using the selected codebook. In generating the QC-LDPC code, the processor may define a plurality of sets of lifting factors, generate a respective table of shift values for each lifting factor of the plurality of sets of lifting factors, and generate the QC-LDPC code using a base matrix and the shift coefficient table.

Abstract: A processor of an apparatus selects a codebook from a plurality of codebooks embedded in a quasi-cyclic-low-density parity-check (QC-LDPC) code. The processor stores the selected codebook in a memory associated with the processor. The processor also encodes data using the selected codebook to generate a plurality of modulation symbols of the data. The processor further controls a transmitter of the apparatus to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus. In selecting the codebook from the plurality of codebooks embedded in the QC-LDPC code, the processor selects the codebook according to one or more rules such that a small codebook requiring a shorter amount of processing latency for the encoding is selected for the encoding unless a larger codebook corresponding to a larger amount of processing latency for the encoding is necessary for the encoding.

Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.

Abstract: A processor of an apparatus establishes a wireless communication link with at least one other apparatus via a transceiver of the apparatus. The processor wirelessly communicates with the other apparatus via the wireless communication link by: selecting a first shift-coefficient table from a plurality of shift-coefficient tables; generating a QC-LDPC code using a base matrix and at least a portion of the first shift-coefficient table; selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code; storing the selected codebook in a memory associated with the processor; encoding data using the selected codebook to generate a plurality of modulation symbols of the data; and controlling the transceiver to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus to transmit the modulation symbols of the data to the other apparatus via the wireless communication link.

Abstract: A processor of an apparatus establishes a wireless communication link with at least one other apparatus via a transceiver of the apparatus. The processor wirelessly communicates with the other apparatus via the wireless communication link by: selecting a first shift-coefficient table from a plurality of shift-coefficient tables; generating a QC-LDPC code using a base matrix and at least a portion of the first shift-coefficient table; selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code; storing the selected codebook in a memory associated with the processor; encoding data using the selected codebook to generate a plurality of modulation symbols of the data; and controlling the transceiver to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus to transmit the modulation symbols of the data to the other apparatus via the wireless communication link.

Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.