Abstract: A device for reading data from a first memory to a second memory based on real-time blank page detection includes a memory controller for reading a page of data from the first memory, a buffer for buffering a portion of the page data, a blank page pre-detection unit for generating a pre-detection result that indicates whether the page is a blank page based on a pre-determined part of the page data, a data processing unit for processing all of the page data to identify a page type, and a control unit for signaling the memory controller to read the page of data from the first memory and enabling the data processing unit based on the pre-detection result.

Abstract: A device for reading data from a first memory to a second memory based on real-time blank page detection includes a memory controller for reading a page of data from the first memory, a buffer for buffering a portion of the page data, a blank page pre-detection unit for generating a pre-detection result that indicates whether the page is a blank page based on a pre-determined part of the page data, a data processing unit for processing all of the page data to identify a page type, and a control unit for signaling the memory controller to read the page of data from the first memory and enabling the data processing unit based on the pre-detection result.

Abstract: A memory system capable of running a variety of different read retry sequences includes a memory controller that has a boot ROM with stored code for executing a read retry sequence. A non-volatile memory device such as a NAND flash includes a read retry register and receives command instructions including a read retry instruction from the memory controller and in response provides read data. A second non-volatile memory that is external to the NAND flash has a read retry table describing read retry sequence items that include a command, a read retry register address, and read retry data for updating the read retry register.

Abstract: A method for conserving power in a computing device having a volatile system memory, a non-volatile storage device, and a processor executing an operating system and including an internal non-volatile memory (NVM). The method includes receiving, at the processor, a request to enter the computing device into a hibernation mode, suspending, by the processor, execution of the operating system, copying, by the processor, substantially the entire contents of the volatile system memory into the non-volatile storage device, storing, in the internal NVM of the processor, a hibernate flag, and turning off power to the computing device.

Abstract: A device for reading data from a first memory to a second memory based on real-time blank page detection includes a memory controller for reading a page of data from the first memory, a buffer for buffering a portion of the page data, a blank page pre-detection unit for generating a pre-detection result that indicates whether the page is a blank page based on a pre-determined part of the page data, a data processing unit for processing all of the page data to identify a page type, and a control unit for signaling the memory controller to read the page of data from the first memory and enabling the data processing unit based on the pre-detection result.

Abstract: A memory system capable of running a variety of different read retry sequences includes a memory controller that has a boot ROM with stored code for executing a read retry sequence. A non-volatile memory device such as a NAND flash includes a read retry register and receives command instructions including a read retry instruction from the memory controller and in response provides read data. A second non-volatile memory that is external to the NAND flash has a read retry table describing read retry sequence items that include a command, a read retry register address, and read retry data for updating the read retry register.

Abstract: A data processing system includes a boot read only memory (ROM) configured to store boot code; one time programmable (OTP) storage circuitry configured to store patch instructions; a random access memory (RAM); and a processor coupled to the boot ROM, the OTP storage circuitry, and the RAM. The processor is configured to: in response to a reset of the data processing system, copy one or more patch instructions from the OTP storage circuitry into the RAM, and during execution of the boot code, execute a patch instruction from the RAM in place of a boot instruction of the boot code.

Abstract: A data processing system includes a boot read only memory (ROM) configured to store boot code; one time programmable (OTP) storage circuitry configured to store patch instructions; a random access memory (RAM); and a processor coupled to the boot ROM, the OTP storage circuitry, and the RAM. The processor is configured to: in response to a reset of the data processing system, copy one or more patch instructions from the OTP storage circuitry into the RAM, and during execution of the boot code, execute a patch instruction from the RAM in place of a boot instruction of the boot code.