Patents by Inventor Chong-han Park

Chong-han Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11139220
    Abstract: A flexible semiconductor package includes a semiconductor chip accommodated in a cavity formed in a substrate, a molding layer covering an entire upper surface of the substrate and the cavity, and a wiring portion including an insulating layer and a redistribution member provided under lower surfaces of the substrate and the semiconductor chip, wherein the molding layer includes a pre-preg in which a resin is impregnated with a glass fabric, and the molding layer and the insulating layer are attached to the semiconductor chip accommodated in the cavity by a roll-to-roll continuous process.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: October 5, 2021
    Assignee: HAESUNG DS CO., LTD.
    Inventors: Jea Won Kim, Chong Han Park, Jong Woo Park
  • Publication number: 20210057301
    Abstract: A flexible semiconductor package includes a semiconductor chip accommodated in a cavity formed in a substrate, a molding layer covering an entire upper surface of the substrate and the cavity, and a wiring portion including an insulating layer and a redistribution member provided under lower surfaces of the substrate and the semiconductor chip, wherein the molding layer includes a pre-preg in which a resin is impregnated with a glass fabric, and the molding layer and the insulating layer are attached to the semiconductor chip accommodated in the cavity by a roll-to-roll continuous process.
    Type: Application
    Filed: April 21, 2020
    Publication date: February 25, 2021
    Inventors: Jea Won KIM, Chong Han PARK, Jong Woo PARK
  • Publication number: 20090266587
    Abstract: Provided is a method of forming a fine pitch in a flexible printed circuit board (FPCB) having an increased adhesive property of wirings and an improved insulating property between the wirings. The method includes etching regions where wirings are to be formed on a base substrate; forming conductive layers on the etched regions; forming a photoresist film on a substrate between the etched regions; forming the wirings by forming the conductive layers on the etched regions to be higher than the substrate; and removing the photoresist film.
    Type: Application
    Filed: April 15, 2009
    Publication date: October 29, 2009
    Applicant: Samsung Techwin Co., Ltd.
    Inventors: Chong-han Park, Byoung-woo Kim