Abstract: A method of fabricating a high-voltage semiconductor device includes the following steps: providing a semiconductor layer; forming a plurality of trenches in the semiconductor layer to define a plurality of pillars of a first conductivity type in the semiconductor layer between adjacent trenches, wherein the trenches extend from a top surface of the semiconductor layer toward a bottom surface of the semiconductor layer; forming a charge compensation layer of a second conductivity type over at least sidewalls of each trench to a predetermined thickness thereby forming a groove in each trench; and substantially filling each groove with a charge compensation plug of the first conductivity type.

Abstract: A MOS-gate power semiconductor device includes: a main device area including an active area and an edge termination area; and an auxiliary device area horizontally formed outside the main device area so as to include one or more diodes. Accordingly, it is possible to protect a circuit from an overcurrent and thus to prevent deterioration and/or destruction of a device due to the overcurrent.

Abstract: A superjunction semiconductor device includes an edge p pillar, an active region, and a termination region. The edge p pillar has a rectangular ring shape with rounded corners. The edge p pillar has an outer region surrounding the active region and an inner region on in the sides of the active region. The active region has active p pillars and active n pillars having vertical stripe shapes. The active p pillars and the active n pillars are alternately arranged horizontally in the active region. The termination region includes termination n pillars and termination p pillars alternately arranged around the edge p pillar.

Abstract: A superjunction semiconductor device includes an edge p pillar, an active region, and a termination region. The edge p pillar has a rectangular ring shape with rounded corners surrounding the active region. The active region includes an active n region and active p pillars having vertical stripe shapes disposed at regular intervals in the active n region. The top and bottom ends of the active p pillars are separated from the edge p pillar. The termination region includes termination n pillars and termination p pillars alternately arranged around the edge p pillar. Surplus p charges that are not used to balance the quantity of p charges and the quantity of n charges among p charges included in the upper and lower parts of the edge p pillar are eliminated or n charges are supplemented to balance the quantity of p charges and the quantity of n charges.

Abstract: A charge-balance power device and a method of manufacturing the charge-balance power device are provided. The charge-balance power device includes: a charge-balance body region in which one or more first conductive type pillars as a first conductive type impurity region and one or more second conductive type pillars as a second conductive type impurity region are arranged; a first conductive type epitaxial layer that is formed on the charge-balance body region; and a transistor region that is formed in the first conductive type epitaxial layer. With this invention, it is possible to form the same charge-balance body region regardless of the structure of the transistor region formed on the top side of wafer.

Abstract: A method of fabricating a high-voltage semiconductor device includes the following steps: providing a semiconductor layer; forming a plurality of trenches in the semiconductor layer to define a plurality of pillars of a first conductivity type in the semiconductor layer between adjacent trenches, wherein the trenches extend from a top surface of the semiconductor layer toward a bottom surface of the semiconductor layer; forming a charge compensation layer of a second conductivity type over at least sidewalls of each trench to a predetermined thickness thereby forming a groove in each trench; and substantially filling each groove with a charge compensation plug of the first conductivity type.

Abstract: A MOS-gate power semiconductor device includes: a main device area including an active area and an edge termination area; and an auxiliary device area horizontally formed outside the main device area so as to include one or more diodes. Accordingly, it is possible to protect a circuit from an overcurrent and thus to prevent deterioration and/or destruction of a device due to the overcurrent.

Abstract: A MOS-gate power semiconductor device is provided which includes: one or more P-type wells formed under one or more of a gate metal electrode and a gate bus line and electrically connected to an emitter metal electrode; and one or more N-type wells formed in the P-type well and electrically connected to one or more of the gate metal electrode and the gate bus line. According to this configuration, it is possible to suppress deterioration and/or destruction of a device due to an overcurrent.

Abstract: A high-voltage semiconductor device includes a semiconductor layer having a plurality of pillars of a first conductivity type defined by a plurality of trenches which extend from a top surface of the semiconductor layer toward a bottom surface thereof. A charge compensation layer of a second conductivity type is disposed over at least sidewalls of each trench to a predetermined thickness to form a groove in each trench. A charge compensation plug of the first conductivity type substantially fills each groove.

Abstract: Provided are a power semiconductor device using a silicon substrate as a FS layer and a method of manufacturing the same. A semiconductor substrate of a first conductivity type is prepared. An epitaxial layer is grown on one surface of the semiconductor substrate. Here, the epitaxial layer is doped at a concentration lower than that of the semiconductor substrate and is intended to be used as a drift region. A base region of a second conductivity type is formed in a predetermined region of the epitaxial layer. An emitter region of the first conductivity type is formed in a predetermined region of the base region. A gate electrode with a gate insulating layer is formed on the base region between the emitter region and the drift region of the epitaxial layer. A rear surface of the semiconductor substrate is ground to reduce the thickness of the semiconductor substrate, thereby setting an FS region of the first conductivity type.

Abstract: A high-voltage semiconductor device includes a semiconductor layer having a plurality of pillars of a first conductivity type defined by a plurality of trenches which extend from a top surface of the semiconductor layer toward a bottom surface thereof. A charge compensation layer of a second conductivity type is disposed over at least sidewalls of each trench to a predetermined thickness to form a groove in each trench. A charge compensation plug of the first conductivity type substantially fills each groove.

Abstract: In accordance with one embodiment of the present invention, a power semiconductor device includes a first drift region of a first conductivity type extending over a semiconductor substrate. The first drift region has a lower impurity concentration than the semiconductor substrate. A second drift region of the first conductivity type extends over the first drift region, and has a higher impurity concentration than the first drift region. A plurality of stripe-shaped body regions of a second conductivity type are formed in an upper portion of the second drift region. A third region of the first conductivity type is formed in an upper portion of each body region so as to form a channel region in each body region between the third region and the second drift region. A gate electrode laterally extends over but is insulated from: (i) the channel region in each body region, (ii) a surface area of the second drift region between adjacent stripes of body regions, and (iii) a surface portion of each source region.

Abstract: Provided are a power semiconductor device using a silicon substrate as a FS layer and a method of manufacturing the same. A semiconductor substrate of a first conductivity type is prepared. An epitaxial layer is grown on one surface of the semiconductor substrate. Here, the epitaxial layer is doped at a concentration lower than that of the semiconductor substrate and is intended to be used as a drift region. A base region of a second conductivity type is formed in a predetermined region of the epitaxial layer. An emitter region of the first conductivity type is formed in a predetermined region of the base region. A gate electrode with a gate insulating layer is formed on the base region between the emitter region and the drift region of the epitaxial layer. A rear surface of the semiconductor substrate is ground to reduce the thickness of the semiconductor substrate, thereby setting an FS region of the first conductivity type.

Abstract: Provided is a high-voltage semiconductor device which is constructed such that the quantity of P and N charges are balanced in the entire drift region thereby preventing the degradation of the device breakdown characteristics. The high-voltage semiconductor device comprises an active region including N pillars of N conductivity type and P pillars of P conductivity type, arranged alternately in a direction from a center portion of the active region to an outer portion thereof to encircle each other in a horizontal direction. The N and P pillars are formed in a closed shape.

Abstract: In accordance with one embodiment of the present invention, a power semiconductor device includes a first drift region of a first conductivity type extending over a semiconductor substrate. The first drift region has a lower impurity concentration than the semiconductor substrate. A second drift region of the first conductivity type extends over the first drift region, and has a higher impurity concentration than the first drift region. A plurality of stripe-shaped body regions of a second conductivity type are formed in an upper portion of the second drift region. A third region of the first conductivity type is formed in an upper portion of each body region so as to form a channel region in each body region between the third region and the second drift region. A gate electrode laterally extends over but is insulated from: (i) the channel region in each body region, (ii) a surface area of the second drift region between adjacent stripes of body regions, and (iii) a surface portion of each source region.

Abstract: In accordance with one embodiment of the present invention, a power semiconductor device includes a first drift region of a first conductivity type extending over a semiconductor substrate. The first drift region has a lower impurity concentration than the semiconductor substrate. A second drift region of the first conductivity type extends over the first drift region, and has a higher impurity concentration than the first drift region. A plurality of stripe-shaped body regions of a second conductivity type are formed in an upper portion of the second drift region. A third region of the first conductivity type is formed in an upper portion of each body region so as to form a channel region in each body region between the third region and the second drift region. A gate electrode laterally extends over but is insulated from: (i) the channel region in each body region, (ii) a surface area of the second drift region between adjacent stripes of body regions, and (iii) a surface portion of each source region.

Abstract: In accordance with the present invention, a transistor includes a semiconductor substrate forming a collector region. A drift region of a first conductivity type extends over the semiconductor substrate. First and second well regions of a second conductivity each extends from an upper surface of the drift region into and terminates within the drift region. The first well region is coupled to an emitter terminal while the second well region floats. The first and second well regions are separated by an impurity region of the first conductivity type such that each of the first and second well regions forms a separate pn junction with the impurity region.

Abstract: In accordance with one embodiment of the present invention, a power semiconductor device includes a first drift region of a first conductivity type extending over a semiconductor substrate. The first drift region has a lower impurity concentration than the semiconductor substrate. A second drift region of the first conductivity type extends over the first drift region, and has a higher impurity concentration than the first drift region. A plurality of stripe-shaped body regions of a second conductivity type are formed in an upper portion of the second drift region. A third region of the first conductivity type is formed in an upper portion of each body region so as to form a channel region in each body region between the third region and the second drift region. A gate electrode laterally extends over but is insulated from: (i) the channel region in each body region, (ii) a surface area of the second drift region between adjacent stripes of body regions, and (iii) a surface portion of each source region.

Abstract: A power MOSFET is provided. In this power MOSFET, a drift region is formed on a drain region having the same conductivity type as that of the drain region using a semiconductor substrate of a first conductivity type. A gate electrode is formed on the drift region, having a plurality of openings spaced apart from each other by a predetermined distance. The plurality of openings partially expose the drift region, and a gate insulating layer is interposed between the gate electrode and the drift region. A body region of a second conductivity type opposite to the first conductivity type is formed on a predetermined upper region of the drift region and extends from the opening to have a side overlapped by the gate electrode. A channel in the portion of the body region overlapped by the gate electrode is not formed and is adjacent to at least two facing sides of the opening.

Abstract: A MOS-gated power semiconductor device is described. The MOS-gated power semiconductor device includes a semiconductor substrate that is heavily doped with impurities of a first conductivity type and used as a collector region, a drift region lightly doped with impurities of a second conductivity type on the substrate, a gate insulating layer on the drift region having a center thicker than its edges, a gate electrode on the gate insulating layer, a well region that is lightly doped with impurities of a first conductivity type on the drift region and that has a channel region overlapping a portion of the gate electrode, an emitter region that is heavily doped with impurities of a second conductivity type and that contacts the channel region, an emitter electrode electrically connected to the emitter region and isolated from the gate electrode, and a collector electrode electrically connected to the semiconductor substrate.