Abstract: An arbiter circuit has a first flip flop and a second flip flop. The first flip flop sends a bus request (BR*) signal to the VME bus by toggling the bus request signal when a trigger signal is received. The second flip flop sends a bus busy (BBSY*) signal to the VME bus by toggling the bus busy signal when a bus grant (BG*) signal is received from the VME bus. The second flip flop releases the bus busy (BBSY*) signal on the VME bus when a reset is commanded at the end of the test by a controller or a push button switch. Tests are performed by writing to the bus and reading from the bus by an address register, a write data register and a read data register connected to the address and data lines of the VME bus. The trigger signal source is selected by a trigger select circuit. A data transfer acknowledge trigger can be selected to trigger every time the data transfer acknowledged (DTACK*) line from the VME bus indicates a data transfer on the bus.

Abstract: An integrated circuit socket is provided with an insulating member and a plurality of conductive socket pins extending from the insulating member. These socket pins are adapted to be electrically connected to the pins of an integrated circuit. A plurality of impedance elements are mechanically supported by the insulating member. Switches are provided for selectively connecting each of the impedance elements to, or isolating each of the impedance elements from, at least one of the socket pins, thereby providing the flexibility to terminate any combination of pins on the integrated circuit.