Patents by Inventor Chooi Mei Chong

Chooi Mei Chong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10204845
    Abstract: A semiconductor chip package includes a semiconductor chip disposed over a main surface of a carrier. An encapsulation body encapsulates the chip. First electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a first side face of the encapsulation body. Second electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a second side face of the encapsulation body opposite the first side face. A first group of the first electrical contact elements and a second group of the first electrical contact elements are spaced apart by a distance D that is greater than a distance P between adjacent first electrical contact elements of the first group and between adjacent first electrical contact elements of the second group. The distances D and P are measured between center axes of electrical contact elements.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: February 12, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Amirul Afiq Hud, Chooi Mei Chong, Josef Hoeglauer, Klaus Schiess, Lee Shuang Wang, Matthias Strassburg, Teck Sim Lee, Xaver Schloegel
  • Patent number: 10147703
    Abstract: In some examples, a device includes a power supply element and a reference voltage element, wherein the reference voltage element is electrically isolated from the power supply element. The device further includes a high-side semiconductor die including at least two high-side transistors, wherein each high-side transistor of the at least two high-side transistors is electrically connected to the power supply element. The device also includes a low-side semiconductor die including at least two low-side transistors, wherein each low-side transistor of the at least two low-side transistors is electrically connected to the reference voltage element. The device includes at least two switching elements, wherein each switching element of the at least two switching elements is electrically connected to a respective high-side transistor of the at least two high-side transistors and to a respective low-side transistor of the at least two low-side transistors.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: December 4, 2018
    Assignee: Infineon Technologies AG
    Inventors: Stefan Macheiner, Amirul Afiq Hud, Teck Sim Lee, Thomas Stoek, Lee Shuang Wang, Chooi Mei Chong, Wei Hing Tan
  • Publication number: 20180301398
    Abstract: A package encloses a power semiconductor die that has a first load terminal at a die frontside facing a footprint side of the package and a second load terminal arranged at a die backside facing a top side of the package. The package also includes a lead frame configured to electrically and mechanically couple the package to a support. The lead frame has a planar first outside terminal electrically connected with the first load terminal and a planar second outside terminal electrically connected with the second load terminal, The planar first outside terminal is configured to interface with the support by means of a first contact area. The planar second outside terminal is configured to interface with the support by means of a second contact area. The second contact area has a size in a range between 80% and 120% of a size of the first contact area.
    Type: Application
    Filed: April 16, 2018
    Publication date: October 18, 2018
    Inventors: Ralf Otremba, Chooi Mei Chong, Markus Dinkel, Josef Hoeglauer, Klaus Schiess, Xaver Schloegel
  • Publication number: 20180277513
    Abstract: In some examples, a device includes a power supply element and a reference voltage element, wherein the reference voltage element is electrically isolated from the power supply element. The device further includes a high-side semiconductor die including at least two high-side transistors, wherein each high-side transistor of the at least two high-side transistors is electrically connected to the power supply element. The device also includes a low-side semiconductor die including at least two low-side transistors, wherein each low-side transistor of the at least two low-side transistors is electrically connected to the reference voltage element. The device includes at least two switching elements, wherein each switching element of the at least two switching elements is electrically connected to a respective high-side transistor of the at least two high-side transistors and to a respective low-side transistor of the at least two low-side transistors.
    Type: Application
    Filed: March 24, 2017
    Publication date: September 27, 2018
    Inventors: Stefan Macheiner, Amirul Afiq Hud, Teck Sim Lee, Thomas Stoek, Lee Shuang Wang, Chooi Mei Chong, Wei Hing Tan
  • Patent number: 10037934
    Abstract: A semiconductor chip package includes a semiconductor chip, an encapsulation body encapsulating the semiconductor chip, a chip pad, and electrical contact elements connected with the semiconductor chip and extending outwardly. The encapsulation body has six side faces and the electrical contact elements extend exclusively through two opposing side faces which have the smallest surface areas from all the side faces. The semiconductor chip is disposed on the chip pad, and a main face of the chip pad remote from the semiconductor chip is at least partially exposed to the outside.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: July 31, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Chooi Mei Chong, Raynold Talavera Corocotchia, Teck Sim Lee, Sanjay Kumar Murugan, Klaus Schiess, Chee Voon Tan, Wee Boon Tay
  • Publication number: 20180158758
    Abstract: A method of manufacturing a hybrid leadframe is provided comprising providing a thin leadframe layer comprising a diepad and a structured region and attaching a metal layer on the diepad, wherein the metal layer has a thickness which is larger than a thickness of the thin leadframe layer.
    Type: Application
    Filed: February 6, 2018
    Publication date: June 7, 2018
    Inventors: Ralf OTREMBA, Chooi Mei Chong, Josef Hoeglauer, Teck Sim Lee, Klaus Schiess, Xaver Schloegel
  • Publication number: 20180061745
    Abstract: A semiconductor chip package includes a semiconductor chip disposed over a main surface of a carrier. An encapsulation body encapsulates the chip. First electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a first side face of the encapsulation body. Second electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a second side face of the encapsulation body opposite the first side face. A first group of the first electrical contact elements and a second group of the first electrical contact elements are spaced apart by a distance D that is greater than a distance P between adjacent first electrical contact elements of the first group and between adjacent first electrical contact elements of the second group. The distances D and P are measured between center axes of electrical contact elements.
    Type: Application
    Filed: August 28, 2017
    Publication date: March 1, 2018
    Inventors: Ralf Otremba, Amirul Afiq Hud, Chooi Mei Chong, Josef Hoeglauer, Klaus Schiess, Lee Shuang Wang, Matthias Strassburg, Teck Sim Lee, Xaver Schloegel
  • Patent number: 9806029
    Abstract: An electronic device comprising a first substrate, a second substrate, a first semiconductor chip comprising a transistor, comprising a first mounting surface bonded to the first substrate and comprising a second mounting surface bonded to the second substrate, and a second semiconductor chip comprising a first mounting surface bonded to the first substrate and comprising a second mounting surface bonded to the second substrate, wherein the first semiconductor chip comprises a via electrically coupling a first transistor terminal at its first mounting surface with a second transistor terminal at its second mounting surface.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: October 31, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Chooi Mei Chong
  • Publication number: 20170047315
    Abstract: A method of manufacturing a semiconductor device includes mounting a first semiconductor power chip on a first carrier, mounting a second semiconductor power chip on a second carrier, bonding a contact clip to the first semiconductor power chip and to the second semiconductor power chip, and mounting a third semiconductor chip over the contact clip.
    Type: Application
    Filed: October 28, 2016
    Publication date: February 16, 2017
    Inventors: Ralf Otremba, Josef Hoeglauer, Xaver Schloegel, Chooi Mei Chong
  • Patent number: 9515060
    Abstract: A semiconductor device includes a first semiconductor power chip mounted over a first carrier and a second semiconductor power chip mounted over a second carrier. The semiconductor device further includes a contact clip mounted over the first semiconductor power chip and on the second semiconductor power chip. A semiconductor logic chip is mounted over the contact clip.
    Type: Grant
    Filed: March 20, 2013
    Date of Patent: December 6, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Xaver Schloegel, Chooi Mei Chong
  • Publication number: 20160233149
    Abstract: A semiconductor chip package includes a semiconductor chip, an encapsulation body encapsulating the semiconductor chip, a chip pad, and electrical contact elements connected with the semiconductor chip and extending outwardly. The encapsulation body has six side faces and the electrical contact elements extend exclusively through two opposing side faces which have the smallest surface areas from all the side faces. The semiconductor chip is disposed on the chip pad, and a main face of the chip pad remote from the semiconductor chip is at least partially exposed to the outside.
    Type: Application
    Filed: February 4, 2016
    Publication date: August 11, 2016
    Inventors: Ralf Otremba, Chooi Mei Chong, Raynold Talavera Corocotchia, Teck Sim Lee, Sanjay Kumar Murugan, Klaus Schiess, Chee Voon Tan, Wee Boon Tay
  • Patent number: 9368435
    Abstract: In an embodiment, an electronic component includes a dielectric layer, a semiconductor device embedded in the dielectric layer, an electrically conductive substrate, a redistribution layer having a first surface and a second surface providing at least one outer contact, and a first electrically conductive member. The semiconductor device has a first surface including at least one first contact pad and a second surface including at least one second contact pad. The second contact pad is mounted on the electrically conductive substrate. The first electrically conductive member includes at least one stud bump and extends between the electrically conductive substrate and the first surface of the redistribution layer.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: June 14, 2016
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Klaus Schiess, Dominic Maier, Chooi Mei Chong
  • Publication number: 20160086876
    Abstract: In an embodiment, an electronic component includes a dielectric layer, a semiconductor device embedded in the dielectric layer, an electrically conductive substrate, a redistribution layer having a first surface and a second surface providing at least one outer contact, and a first electrically conductive member. The semiconductor device has a first surface including at least one first contact pad and a second surface including at least one second contact pad. The second contact pad is mounted on the electrically conductive substrate. The first electrically conductive member includes at least one stud bump and extends between the electrically conductive substrate and the first surface of the redistribution layer.
    Type: Application
    Filed: September 23, 2014
    Publication date: March 24, 2016
    Inventors: Ralf Otremba, Klaus Schiess, Dominic Maier, Chooi Mei Chong
  • Publication number: 20160056092
    Abstract: A hybrid leadframe is provided comprising a thin leadframe layer comprising a diepad and a structured region; and a metal layer being thicker than the thin leadframe layer and arranged on the diepad.
    Type: Application
    Filed: August 19, 2015
    Publication date: February 25, 2016
    Inventors: Ralf OTREMBA, Chooi Mei CHONG, Josef HOEGLAUER, Teck Sim LEE, Klaus SCHIESS, Xaver SCHLOEGEL
  • Patent number: 9041170
    Abstract: A semiconductor package includes a semiconductor die having a first electrode at a first side and a second electrode at a second side opposing the first side, a first lead under the semiconductor die and connected to the first electrode at a first level of the package, and a second lead having a height greater than the first lead and terminating at a second level in the package above the first level, the second level corresponding to a height of the semiconductor die. A connector of a single continuous planar construction over the semiconductor die and the second lead is connected to both the second electrode and the second lead at the same second level of the package.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Josef Höglauer, Klaus Schiess, Chooi Mei Chong
  • Publication number: 20150092375
    Abstract: An electronic device comprising a first substrate, a second substrate, a first semiconductor chip comprising a transistor, comprising a first mounting surface bonded to the first substrate and comprising a second mounting surface bonded to the second substrate, and a second semiconductor chip comprising a first mounting surface bonded to the first substrate and comprising a second mounting surface bonded to the second substrate, wherein the first semiconductor chip comprises a via electrically coupling a first transistor terminal at its first mounting surface with a second transistor terminal at its second mounting surface.
    Type: Application
    Filed: October 2, 2013
    Publication date: April 2, 2015
    Applicant: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Chooi Mei Chong
  • Patent number: 8975117
    Abstract: A method includes providing a semiconductor chip having a first main surface and a second main surface. A semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. A first layer of solder material is provided between the first main surface and the carrier. A contact clip including a first contact area is placed on the semiconductor chip with the first contact area facing the second main surface of the semiconductor chip. A second layer of solder material is provided between the first contact area and the second main surface. Thereafter, heat is applied to the first and second layers of solder material to form diffusion solder bonds between the carrier, the semiconductor chip and the contact clip.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: March 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Fong Lim, Abdul Rahman Mohamed, Chooi Mei Chong, Ida Fischbach, Xaver Schloegel, Juergen Schredl, Josef Hoeglauer
  • Patent number: 8853835
    Abstract: A chip package is provided. The chip package includes a chip carrier, a voltage supply lead, a sensing terminal and a chip disposed over the chip carrier. The chip includes a first terminal and a second terminal, wherein the first terminal electrically contacts the chip carrier. The chip package also includes an electrically conductive element formed over the second terminal, the electrically conductive element electrically coupling the second terminal to the voltage supply lead and the sensing terminal.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: October 7, 2014
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Gerhard Noebauer, Chooi Mei Chong
  • Publication number: 20140291849
    Abstract: A semiconductor package includes a semiconductor die having a first electrode at a first side and a second electrode at a second side opposing the first side, a first lead under the semiconductor die and connected to the first electrode at a first level of the package, and a second lead having a height greater than the first lead and terminating at a second level in the package above the first level, the second level corresponding to a height of the semiconductor die. A connector of a single continuous planar construction over the semiconductor die and the second lead is connected to both the second electrode and the second lead at the same second level of the package.
    Type: Application
    Filed: April 2, 2013
    Publication date: October 2, 2014
    Applicant: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Josef Höglauer, Klaus Schiess, Chooi Mei Chong
  • Patent number: 8836101
    Abstract: Semiconductor packages and method of fabricating them are described. In one embodiment, the semiconductor package includes a substrate having a first and a second die attach pad. A first die is disposed over the first die attach pad. A second die is disposed over the second die attach pad. A third die is disposed between the first and the second die. The third die having a first, a second, and a third portion such that the first portion is disposed above a portion of the first die, the second portion is disposed above a portion of the second die, and the third portion is disposed above an area between the first die and the second die.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: September 16, 2014
    Assignee: Infineon Technologies AG
    Inventors: Chooi Mei Chong, Teck Sim Lee