Patents by Inventor Chooi Mei Chong
Chooi Mei Chong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11869865Abstract: A semiconductor device includes: a carrier having a die pad and a contact; a semiconductor die having opposing first and second main sides and being attached to the die pad by a first solder joint such that the second main side faces the die pad; and a contact clip having a first contact region and a second contact region. The first contact is attached to the first main side by a second solder joint. The second contact region is attached to the contact by a third solder joint. The first contact region has a convex shape facing towards the first main side such that a distance between the first main side and the first contact region increases from a base of the convex shape towards an edge of the first contact region. The base runs along a line that is substantially perpendicular to a longitudinal axis of the contact clip.Type: GrantFiled: July 30, 2021Date of Patent: January 9, 2024Assignee: Infineon Technologies AGInventors: Thomas Bemmerl, Chooi Mei Chong, Edward Myers, Michael Stadler
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Patent number: 11211356Abstract: A power semiconductor package includes a power semiconductor chip, an electrical connector arranged at a first side of the power semiconductor chip and having a first surface that is coupled to a power electrode of the power semiconductor chip, an encapsulation body at least partially encapsulating the power semiconductor chip and the electrical connector, and an electrical insulation layer arranged at a second surface of the electrical connector opposite the first surface, wherein parts of the encapsulation body and the electrical insulation layer form a coplanar surface of the power semiconductor package.Type: GrantFiled: August 12, 2020Date of Patent: December 28, 2021Assignee: Infineon Technologies AGInventors: Wee Aun Jason Lim, Paul Armand Asentista Calo, Ting Soon Chin, Chooi Mei Chong, Sanjay Kumar Murugan, Ying Pok Sam, Chee Voon Tan
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Publication number: 20210358877Abstract: A semiconductor device includes: a carrier having a die pad and a contact; a semiconductor die having opposing first and second main sides and being attached to the die pad by a first solder joint such that the second main side faces the die pad; and a contact clip having a first contact region and a second contact region. The first contact is attached to the first main side by a second solder joint. The second contact region is attached to the contact by a third solder joint. The first contact region has a convex shape facing towards the first main side such that a distance between the first main side and the first contact region increases from a base of the convex shape towards an edge of the first contact region. The base runs along a line that is substantially perpendicular to a longitudinal axis of the contact clip.Type: ApplicationFiled: July 30, 2021Publication date: November 18, 2021Inventors: Thomas Bemmerl, Chooi Mei Chong, Edward Myers, Michael Stadler
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Patent number: 11088105Abstract: A semiconductor device includes: a carrier having a die pad and a contact; a semiconductor die having opposing first and second main sides and being attached to the die pad by a first solder joint such that the second main side faces the die pad; and a contact clip having a first contact region and a second contact region. The first contact is attached to the first main side by a second solder joint. The second contact region is attached to the contact by a third solder joint. The first contact region has a convex shape facing towards the first main side such that a distance between the first main side and the first contact region increases from a base of the convex shape towards an edge of the first contact region. The base runs along a line that is substantially perpendicular to a longitudinal axis of the contact clip.Type: GrantFiled: November 26, 2019Date of Patent: August 10, 2021Assignee: Infineon Technologies AGInventors: Thomas Bemmerl, Chooi Mei Chong, Edward Myers, Michael Stadler
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Publication number: 20210057375Abstract: A power semiconductor package includes a power semiconductor chip, an electrical connector arranged at a first side of the power semiconductor chip and having a first surface that is coupled to a power electrode of the power semiconductor chip, an encapsulation body at least partially encapsulating the power semiconductor chip and the electrical connector, and an electrical insulation layer arranged at a second surface of the electrical connector opposite the first surface, wherein parts of the encapsulation body and the electrical insulation layer form a coplanar surface of the power semiconductor package.Type: ApplicationFiled: August 12, 2020Publication date: February 25, 2021Inventors: Wee Aun Jason Lim, Paul Armand Asentista Calo, Ting Soon Chin, Chooi Mei Chong, Sanjay Kumar Murugan, Ying Pok Sam, Chee Voon Tan
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Patent number: 10699987Abstract: A package encloses a power semiconductor die that has a first load terminal at a die frontside facing a footprint side of the package and a second load terminal arranged at a die backside facing a top side of the package. The package also includes a lead frame configured to electrically and mechanically couple the package to a support. The lead frame has a planar first outside terminal electrically connected with the first load terminal and a planar second outside terminal electrically connected with the second load terminal. The planar first outside terminal is configured to interface with the support by means of a first contact area. The planar second outside terminal is configured to interface with the support by means of a second contact area. The second contact area has a size in a range between 80% and 120% of a size of the first contact area.Type: GrantFiled: April 16, 2018Date of Patent: June 30, 2020Assignee: tInfineon Technologies Austria AGInventors: Ralf Otremba, Chooi Mei Chong, Markus Dinkel, Josef Hoeglauer, Klaus Schiess, Xaver Schloegel
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Publication number: 20200168575Abstract: A semiconductor device includes: a carrier having a die pad and a contact; a semiconductor die having opposing first and second main sides and being attached to the die pad by a first solder joint such that the second main side faces the die pad; and a contact clip having a first contact region and a second contact region. The first contact is attached to the first main side by a second solder joint. The second contact region is attached to the contact by a third solder joint. The first contact region has a convex shape facing towards the first main side such that a distance between the first main side and the first contact region increases from a base of the convex shape towards an edge of the first contact region. The base runs along a line that is substantially perpendicular to a longitudinal axis of the contact clip.Type: ApplicationFiled: November 26, 2019Publication date: May 28, 2020Inventors: Thomas Bemmerl, Chooi Mei Chong, Edward Myers, Michael Stadler
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Publication number: 20200083207Abstract: A method of manufacturing a semiconductor device includes mounting a first semiconductor power chip on a first carrier, mounting a second semiconductor power chip on a second carrier, bonding a contact clip to the first semiconductor power chip and to the second semiconductor power chip, and mounting a third semiconductor chip over the contact clip.Type: ApplicationFiled: November 14, 2019Publication date: March 12, 2020Inventors: Ralf Otremba, Josef Hoeglauer, Xaver Schloegel, Chooi Mei Chong
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Patent number: 10204845Abstract: A semiconductor chip package includes a semiconductor chip disposed over a main surface of a carrier. An encapsulation body encapsulates the chip. First electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a first side face of the encapsulation body. Second electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a second side face of the encapsulation body opposite the first side face. A first group of the first electrical contact elements and a second group of the first electrical contact elements are spaced apart by a distance D that is greater than a distance P between adjacent first electrical contact elements of the first group and between adjacent first electrical contact elements of the second group. The distances D and P are measured between center axes of electrical contact elements.Type: GrantFiled: August 28, 2017Date of Patent: February 12, 2019Assignee: Infineon Technologies Austria AGInventors: Ralf Otremba, Amirul Afiq Hud, Chooi Mei Chong, Josef Hoeglauer, Klaus Schiess, Lee Shuang Wang, Matthias Strassburg, Teck Sim Lee, Xaver Schloegel
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Patent number: 10147703Abstract: In some examples, a device includes a power supply element and a reference voltage element, wherein the reference voltage element is electrically isolated from the power supply element. The device further includes a high-side semiconductor die including at least two high-side transistors, wherein each high-side transistor of the at least two high-side transistors is electrically connected to the power supply element. The device also includes a low-side semiconductor die including at least two low-side transistors, wherein each low-side transistor of the at least two low-side transistors is electrically connected to the reference voltage element. The device includes at least two switching elements, wherein each switching element of the at least two switching elements is electrically connected to a respective high-side transistor of the at least two high-side transistors and to a respective low-side transistor of the at least two low-side transistors.Type: GrantFiled: March 24, 2017Date of Patent: December 4, 2018Assignee: Infineon Technologies AGInventors: Stefan Macheiner, Amirul Afiq Hud, Teck Sim Lee, Thomas Stoek, Lee Shuang Wang, Chooi Mei Chong, Wei Hing Tan
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Publication number: 20180301398Abstract: A package encloses a power semiconductor die that has a first load terminal at a die frontside facing a footprint side of the package and a second load terminal arranged at a die backside facing a top side of the package. The package also includes a lead frame configured to electrically and mechanically couple the package to a support. The lead frame has a planar first outside terminal electrically connected with the first load terminal and a planar second outside terminal electrically connected with the second load terminal, The planar first outside terminal is configured to interface with the support by means of a first contact area. The planar second outside terminal is configured to interface with the support by means of a second contact area. The second contact area has a size in a range between 80% and 120% of a size of the first contact area.Type: ApplicationFiled: April 16, 2018Publication date: October 18, 2018Inventors: Ralf Otremba, Chooi Mei Chong, Markus Dinkel, Josef Hoeglauer, Klaus Schiess, Xaver Schloegel
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Publication number: 20180277513Abstract: In some examples, a device includes a power supply element and a reference voltage element, wherein the reference voltage element is electrically isolated from the power supply element. The device further includes a high-side semiconductor die including at least two high-side transistors, wherein each high-side transistor of the at least two high-side transistors is electrically connected to the power supply element. The device also includes a low-side semiconductor die including at least two low-side transistors, wherein each low-side transistor of the at least two low-side transistors is electrically connected to the reference voltage element. The device includes at least two switching elements, wherein each switching element of the at least two switching elements is electrically connected to a respective high-side transistor of the at least two high-side transistors and to a respective low-side transistor of the at least two low-side transistors.Type: ApplicationFiled: March 24, 2017Publication date: September 27, 2018Inventors: Stefan Macheiner, Amirul Afiq Hud, Teck Sim Lee, Thomas Stoek, Lee Shuang Wang, Chooi Mei Chong, Wei Hing Tan
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Patent number: 10037934Abstract: A semiconductor chip package includes a semiconductor chip, an encapsulation body encapsulating the semiconductor chip, a chip pad, and electrical contact elements connected with the semiconductor chip and extending outwardly. The encapsulation body has six side faces and the electrical contact elements extend exclusively through two opposing side faces which have the smallest surface areas from all the side faces. The semiconductor chip is disposed on the chip pad, and a main face of the chip pad remote from the semiconductor chip is at least partially exposed to the outside.Type: GrantFiled: February 4, 2016Date of Patent: July 31, 2018Assignee: Infineon Technologies Austria AGInventors: Ralf Otremba, Chooi Mei Chong, Raynold Talavera Corocotchia, Teck Sim Lee, Sanjay Kumar Murugan, Klaus Schiess, Chee Voon Tan, Wee Boon Tay
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Publication number: 20180158758Abstract: A method of manufacturing a hybrid leadframe is provided comprising providing a thin leadframe layer comprising a diepad and a structured region and attaching a metal layer on the diepad, wherein the metal layer has a thickness which is larger than a thickness of the thin leadframe layer.Type: ApplicationFiled: February 6, 2018Publication date: June 7, 2018Inventors: Ralf OTREMBA, Chooi Mei Chong, Josef Hoeglauer, Teck Sim Lee, Klaus Schiess, Xaver Schloegel
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Publication number: 20180061745Abstract: A semiconductor chip package includes a semiconductor chip disposed over a main surface of a carrier. An encapsulation body encapsulates the chip. First electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a first side face of the encapsulation body. Second electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a second side face of the encapsulation body opposite the first side face. A first group of the first electrical contact elements and a second group of the first electrical contact elements are spaced apart by a distance D that is greater than a distance P between adjacent first electrical contact elements of the first group and between adjacent first electrical contact elements of the second group. The distances D and P are measured between center axes of electrical contact elements.Type: ApplicationFiled: August 28, 2017Publication date: March 1, 2018Inventors: Ralf Otremba, Amirul Afiq Hud, Chooi Mei Chong, Josef Hoeglauer, Klaus Schiess, Lee Shuang Wang, Matthias Strassburg, Teck Sim Lee, Xaver Schloegel
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Patent number: 9806029Abstract: An electronic device comprising a first substrate, a second substrate, a first semiconductor chip comprising a transistor, comprising a first mounting surface bonded to the first substrate and comprising a second mounting surface bonded to the second substrate, and a second semiconductor chip comprising a first mounting surface bonded to the first substrate and comprising a second mounting surface bonded to the second substrate, wherein the first semiconductor chip comprises a via electrically coupling a first transistor terminal at its first mounting surface with a second transistor terminal at its second mounting surface.Type: GrantFiled: October 2, 2013Date of Patent: October 31, 2017Assignee: Infineon Technologies Austria AGInventors: Ralf Otremba, Josef Hoeglauer, Chooi Mei Chong
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Publication number: 20170047315Abstract: A method of manufacturing a semiconductor device includes mounting a first semiconductor power chip on a first carrier, mounting a second semiconductor power chip on a second carrier, bonding a contact clip to the first semiconductor power chip and to the second semiconductor power chip, and mounting a third semiconductor chip over the contact clip.Type: ApplicationFiled: October 28, 2016Publication date: February 16, 2017Inventors: Ralf Otremba, Josef Hoeglauer, Xaver Schloegel, Chooi Mei Chong
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Patent number: 9515060Abstract: A semiconductor device includes a first semiconductor power chip mounted over a first carrier and a second semiconductor power chip mounted over a second carrier. The semiconductor device further includes a contact clip mounted over the first semiconductor power chip and on the second semiconductor power chip. A semiconductor logic chip is mounted over the contact clip.Type: GrantFiled: March 20, 2013Date of Patent: December 6, 2016Assignee: Infineon Technologies Austria AGInventors: Ralf Otremba, Josef Hoeglauer, Xaver Schloegel, Chooi Mei Chong
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Publication number: 20160233149Abstract: A semiconductor chip package includes a semiconductor chip, an encapsulation body encapsulating the semiconductor chip, a chip pad, and electrical contact elements connected with the semiconductor chip and extending outwardly. The encapsulation body has six side faces and the electrical contact elements extend exclusively through two opposing side faces which have the smallest surface areas from all the side faces. The semiconductor chip is disposed on the chip pad, and a main face of the chip pad remote from the semiconductor chip is at least partially exposed to the outside.Type: ApplicationFiled: February 4, 2016Publication date: August 11, 2016Inventors: Ralf Otremba, Chooi Mei Chong, Raynold Talavera Corocotchia, Teck Sim Lee, Sanjay Kumar Murugan, Klaus Schiess, Chee Voon Tan, Wee Boon Tay
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Patent number: 9368435Abstract: In an embodiment, an electronic component includes a dielectric layer, a semiconductor device embedded in the dielectric layer, an electrically conductive substrate, a redistribution layer having a first surface and a second surface providing at least one outer contact, and a first electrically conductive member. The semiconductor device has a first surface including at least one first contact pad and a second surface including at least one second contact pad. The second contact pad is mounted on the electrically conductive substrate. The first electrically conductive member includes at least one stud bump and extends between the electrically conductive substrate and the first surface of the redistribution layer.Type: GrantFiled: September 23, 2014Date of Patent: June 14, 2016Assignee: Infineon Technologies AGInventors: Ralf Otremba, Klaus Schiess, Dominic Maier, Chooi Mei Chong