Abstract: A method and system method for communication port management in a device. The method including enabling a set of communication ports in response to power up of the device, detecting connection at a port in the set of communication ports prior to operating system boot of the device, and connecting an external device to an operational component of the device in response to the connection at the port.

Abstract: Embodiments may include systems and methods for communication including a plurality of controllers and coordination circuitry, to control communication to or from an interface circuitry. The interface circuitry includes a plurality of pins, where a first group of pins of the plurality of pins is for a first communication protocol, and a second group of pins of the plurality of pins is for a second communication protocol. A first controller is coupled to the interface circuitry through the first group of pins, and a second controller is coupled to the interface circuitry through the second group of pins. The coordination circuitry is to select the first controller or the second controller to control communication to or from the interface circuitry. Other embodiments may be described and/or claimed.

Abstract: A method and system method for communication port management in a device. The method including enabling a set of communication ports in response to power up of the device, detecting connection at a port in the set of communication ports prior to operating system boot of the device, and connecting an external device to an operational component of the device in response to the connection at the port.

Abstract: Embodiments may include systems and methods for communication including a plurality of controllers and coordination circuitry, to control communication to or from an interface circuitry. The interface circuitry includes a plurality of pins, where a first group of pins of the plurality of pins is for a first communication protocol, and a second group of pins of the plurality of pins is for a second communication protocol. A first controller is coupled to the interface circuitry through the first group of pins, and a second controller is coupled to the interface circuitry through the second group of pins. The coordination circuitry is to select the first controller or the second controller to control communication to or from the interface circuitry. Other embodiments may be described and/or claimed.

Abstract: Translation circuitry for facilitating communication between a protocol stack for a PCIe™ communication protocol and a PHY layer for a low power communication standard. In an embodiment, the translation circuitry includes logic is to variously convert signaling between two or more PHY interface standards. The one or more a PHY interface standards may include a PHY Interface for PCI Express (PIPE) specification and a standard for a comparatively low power communication protocol. In another embodiment, the low power communication standard is a Reference M-PHY Module Interface (RMMI) specification.

Abstract: According to some embodiments, a communication interface 110 may include a biasing circuit 140 and a logic unit 130. The biasing circuit 140 may be configured to provide a bias voltage to a port of the communication interface 110. The logic unit 130 may be configured to enable and disable the biasing circuit 140 based on a first signal received from a controller of the communication interface 110. The logic unit 130 may also be configured to enable and disable the biasing circuit 140 based on a suspend signal received from the controller of the communication interface 110.

Abstract: According to some embodiments, a communication interface 110 may include a biasing circuit 140 and a logic unit 130. The biasing circuit 140 may be configured to provide a bias voltage to a port of the communication interface 110. The logic unit 130 may be configured to enable and disable the biasing circuit 140 based on a first signal received from a controller of the communication interface 110. The logic unit 130 may also be configured to enable and disable the biasing circuit 140 based on a suspend signal received from the controller of the communication interface 110.

Abstract: A power source device supplies power to a host for charging a finite power source of the host. The power is supplied through an interface connecting the host device. The interface may be a Universal Serial Bus (USB) cable or another type of local connection cable.

Abstract: An apparatus may include a processor and first logic operable on the processor to output a direct memory access (DMA) activity indicator to indicate a current state of activity of direct memory access data transfer operations. The apparatus may further include second logic operable on the processor to determine scheduled DMA activity to be performed; and third logic operable on the processor to output a pre-wake indicator to a controller before the scheduled DMA activity is to be performed, to satisfy both Quality of Service (QOS) and Power saving needs. Other embodiments are disclosed and claimed.

Abstract: Embodiments of the invention utilize a universal serial bus (USB) host controller to traverse an asynchronous data transfer list to identify data transfers to execute. The asynchronous data transfer list may include a plurality of header nodes, each header node to identify data transfers to one of a plurality of devices operatively coupled to an electronic device. The USB host controller may execute an extended sleep mode in response to identifying no data transfers to execute and receiving an indication that the system processor is in a sleep state. The USB host controller may exit the extended sleep mode in response to receiving an indication that the processor is in non-sleep state.

Abstract: A power source device supplies power to a host for charging a finite power source of the host. The power is supplied through an interface connecting the host device. The interface may be a Universal Serial Bus (USB) cable or another type of local connection cable.

Abstract: Embodiments of the invention utilize a universal serial bus (USB) host controller to traverse an asynchronous data transfer list to identify data transfers to execute. The asynchronous data transfer list may include a plurality of header nodes, each header node to identify data transfers to one of a plurality of devices operatively coupled to an electronic device. The USB host controller may execute an extended sleep mode in response to identifying no data transfers to execute and receiving an indication that the system processor is in a sleep state. The USB host controller may exit the extended sleep mode in response to receiving an indication that the processor is in non-sleep state.

Abstract: A method, device, system, and computer readable medium are disclosed. In one embodiment the method includes dynamically associating a newly active port in a computer system with a first host controller. The first association happens when a total number of currently active ports in the computer system is less than a maximum capacity number of ports for the first host controller. The method also includes dynamically associating the newly active port in the computer system with a second host controller. The second association happens when the total number of currently active ports in the computer system is greater than or equal to the maximum capacity number of ports for the first host controller. In this method, each port, the first host controller, and second host controller all utilize the same protocol.

Abstract: A method, device, system, and computer readable medium are disclosed. In one embodiment the method includes dynamically associating a newly active port in a computer system with a first host controller. The first association happens when a total number of currently active ports in the computer system is less than a maximum capacity number of ports for the first host controller. The method also includes dynamically associating the newly active port in the computer system with a second host controller. The second association happens when the total number of currently active ports in the computer system is greater than or equal to the maximum capacity number of ports for the first host controller. In this method, each port, the first host controller, and second host controller all utilize the same protocol.