Patents by Inventor Choon Hwan Kim

Choon Hwan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7935591
    Abstract: Provided are a method for fabricating a PMOS transistor and a method for forming a dual gate of a semiconductor device using the same. The method for fabricating a PMOS transistor includes forming a gate insulation layer over a semiconductor substrate; forming a polysilicon layer over the gate insulation layer; and doping the polysilicon layer using a boron (B) containing gas in one of an Atomic Layer Deposition (ALD) chamber and a Chemical Vapor Deposition (CVD) chamber.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: May 3, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyoung Bong Rouh, Choon Hwan Kim, Il Cheol Rho
  • Publication number: 20100120240
    Abstract: Provided are a method for fabricating a PMOS transistor and a method for forming a dual gate of a semiconductor device using the same. The method for fabricating a PMOS transistor includes forming a gate insulation layer over a semiconductor substrate; forming a polysilicon layer over the gate insulation layer; and doping the polysilicon layer using a boron (B) containing gas in one of an Atomic Layer Deposition (ALD) chamber and a Chemical Vapor Deposition (CVD) chamber.
    Type: Application
    Filed: December 30, 2008
    Publication date: May 13, 2010
    Applicant: Hynix Semiconductor Inc.
    Inventors: Kyoung Bong Rouh, Choon Hwan Kim, Il Cheol Rho
  • Patent number: 7563718
    Abstract: A semiconductor substrate is loaded into a reaction chamber to form a tungsten layer. A source gas including tungsten (W) is introduced into the reaction chamber to grow a crystal nucleus of the tungsten on the semiconductor substrate. A reduction gas containing boron (B) is introduced into the reaction chamber to form a tungsten layer on the semiconductor substrate by actions of the source gas and the reduction gas. A hydrogen (H2) gas is introduced into the reaction chamber to remove the boron (B) remaining in the tungsten layer.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: July 21, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Choon Hwan Kim
  • Publication number: 20090170311
    Abstract: A method for fabricating a contact in a semiconductor device includes forming an insulating film having a contact hole over a bottom film, forming a thin metal film in the exposed portion of the bottom film by supplying a reaction gas containing a metal component to a surface of the bottom film exposed by the contact hole, forming a metal silicide film by performing an annealing process on the thin metal film, and forming a metal film over the metal silicide film to fill the contact hole.
    Type: Application
    Filed: December 30, 2008
    Publication date: July 2, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Choon Hwan Kim, Kyoung Bong Routh, II Cheol Rho
  • Publication number: 20090004848
    Abstract: A method for fabricating an interconnection in a semiconductor device includes forming a hydrogenated tungsten nucleation layer on a semiconductor substrate, and forming a bulk tungsten layer on the tungsten nucleation layer. Boron ions react with a hydrogen gas supplied together with a diborane gas to be restored to a diborane again, thereby preventing a boron layer from being formed on an interface of the tungsten nucleation layer.
    Type: Application
    Filed: December 6, 2007
    Publication date: January 1, 2009
    Inventors: Choon Hwan Kim, II Cheol Rho
  • Publication number: 20080233742
    Abstract: A contact hole is formed in an interlayer insulating layer disposed on a semiconductor substrate. The semiconductor substrate is loaded into a reaction chamber. A reaction gas including an aluminum precursor is injected into the reaction chamber. Reaction energy is supplied to the reaction chamber so as to allow thermal decomposition of the aluminum precursor. The injecting of the reaction gas and the supplying of the reaction energy are periodically repeated to deposit a first aluminum layer on the semiconductor substrate. A second aluminum layer is deposited to fill the contact hole.
    Type: Application
    Filed: December 5, 2007
    Publication date: September 25, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Choon Hwan KIM, II Cheol Rho
  • Patent number: 7332391
    Abstract: A method for forming storage node contacts in a semiconductor device includes forming an interlayer dielectric layer on a semiconductor substrate provided with transistors; forming a hydrogen diffusion preventing layer on the interlayer dielectric layer; forming a hard mask layer containing hydrogen atoms on the hydrogen diffusion preventing layer; forming storage node contact holes, which pass through the hydrogen diffusion preventing layer and the interlayer dielectric layer and expose impurity regions of the transistors, by etching the hydrogen diffusion preventing layer and the interlayer dielectric layer using the hard mask layer as an etching barrier layer; and forming the storage node contacts by filling the storage node contact holes with a conductive layer.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: February 19, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventors: Il Cheol Roh, Choon Hwan Kim
  • Publication number: 20080003797
    Abstract: A semiconductor substrate is loaded into a reaction chamber to form a tungsten layer. A source gas including tungsten (W) is introduced into the reaction chamber to grow a crystal nucleus of the tungsten on the semiconductor substrate. A reduction gas containing boron (B) is introduced into the reaction chamber to form a tungsten layer on the semiconductor substrate by actions of the source gas and the reduction gas. A hydrogen (H2) gas is introduced into the reaction chamber to remove the boron (B) remaining in the tungsten layer.
    Type: Application
    Filed: December 29, 2006
    Publication date: January 3, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventor: Choon Hwan Kim
  • Publication number: 20070259492
    Abstract: A method for forming storage node contacts in a semiconductor device includes forming an interlayer dielectric layer on a semiconductor substrate provided with transistors; forming a hydrogen diffusion preventing layer on the interlayer dielectric layer; forming a hard mask layer containing hydrogen atoms on the hydrogen diffusion preventing layer; forming storage node contact holes, which pass through the hydrogen diffusion preventing layer and the interlayer dielectric layer and expose impurity regions of the transistors, by etching the hydrogen diffusion preventing layer and the interlayer dielectric layer using the hard mask layer as an etching barrier layer; and forming the storage node contacts by filling the storage node contact holes with a conductive layer.
    Type: Application
    Filed: December 29, 2006
    Publication date: November 8, 2007
    Applicant: Hynix Semiconductor Inc.
    Inventors: Il Cheol Roh, Choon Hwan Kim
  • Patent number: 5940730
    Abstract: The present invention relates to a method of forming a contact hole of a semiconductor device, and discloses a method of forming a contact hole of a semiconductor device which can remove an oxide film formed on the bottom of the contact hole, and make the edge portions of the entrance to the contact hole and reduce the topology of the contact hole by performing high frequency plasma etching processes in two stage in which the condition of pressure and electric power are different.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: August 17, 1999
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Noh Jung Kwak, Choon Hwan Kim
  • Patent number: 5702568
    Abstract: The present invention discloses a method of forming a via hole of a semiconductor device, which includes the steps of: forming a plurality of first metal wires on a wafer; after coating a SOG film on the first oxide film, forming a groove in the SOG film using a mask in which a via hole contact is formed, the size of which is bigger than that of the real via hole to be formed in it; performing a process of filling up completely the groove portion (a two-step process for the first embodiment or a one-step process for the second embodiment); and forming a via hole using a contact mask the size of which is the same as that of the real via hole.
    Type: Grant
    Filed: June 24, 1996
    Date of Patent: December 30, 1997
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Chan Soo Shin, Choon Hwan Kim