Abstract: A method of executing a fused instruction is disclosed. The method begins by performing several actions, which may be performed serially or in parallel. These include performing a floating point multiplication of a first floating point number by a second floating point number and normalizing a third floating point number. The floating point multiplication of the first and second floating point numbers generates a first result, while the normalization generates a second result. The first result is then added to the second result, generating an unnormalized result. A determination is also made as to whether a large exponent difference exists between the first result and the second result. If a large exponent difference exists between the first result and the second result, a large exponent difference normalization is performed on the unnormalized result. Otherwise, a small exponent difference normalization is performed on the unnormalized result.

Abstract: Disclosed herein is an apparatus and method for determining if a first number is greater than or equal to a second number. By analyzing nibbles of a multi-bit number in parallel to determine for each nibble if the nibbles are unequal and if a first nibble is greater than a second nibble and thereafter logically determining which of the highest order nibbles, if any, are unequal to discover whether the first number is greater than the second number, or determining that all nibble pairs are equal and thus concluding that both numbers are equal. A digital logic circuit is preferably employed for such analysis.

Abstract: An abstract register transfer level (RTL) model that simulates behavior of a dynamic circuit is created. The model is built upon an existing RTL with another level of abstraction capturing input transitions.

Abstract: A fused instruction datapath is disclosed. The fused instruction datapath may include a normalization unit, a floating point mutltiplier coupled to the normalization unit, and a mantissa alignment unit coupled to provide an aligned mantissa to the floating point multiplier. The floating point multiplier may include a term generation unit and a compensation unit coupled to the term generation unit. The term generation unit may be configured to generate a sum term and a carry term. The compensation unit may be configured to compensate the sum term.

Abstract: A double-precision multiplier for use in the floating point pipeline of a processor has an array multiplier and a carry-save partial-product accumulator. Double precision multiplication is accomplished by generating a plurality of partial products and summing these in the carry-save partial-product accumulator. The partial-product accumulator has a carry-save adder, a sum register, a carry-out counter and an extender. The carry-out counter receives a carry outputs of the carry-save adder and array multiplier, and the extender is coupled to extend the sum register dependent upon the contents of the carry-out counter. The extension occurs during addition of the most significant partial product to the sum of less significant partial products.

Abstract: An abstract register transfer level (RTL) model that simulates behavior of a dynamic circuit is created. The model is built upon an existing RTL with another level of abstraction capturing input transitions.

Abstract: A double-precision multiplier for use in the floating point pipeline of a processor has an array multiplier and a carry-save partial-product accumulator. Double precision multiplication is accomplished by generating a plurality of partial products and summing these in the carry-save partial-product accumulator. The partial-product accumulator has a carry-save adder, a sum register, a carry-out counter and an extender. The carry-out counter receives a carry outputs of the carry-save adder and array multiplier, and the extender is coupled to extend the sum register dependent upon the contents of the carry-out counter. The extension occurs during addition of the most significant partial product to the sum of less significant partial products.

Abstract: A double-precision multiplier for use in the floating point pipeline of a processor has an array multiplier and a carry-save partial-product accumulator. Double precision multiplication is accomplished by generating a plurality of partial products and summing these in the carry-save partial-product accumulator. The partial-product accumulator has a carry-save adder, a sum register, a carry-out counter and an extender. The carry-out counter receives a carry outputs of the carry-save adder and array multiplier, and the extender is coupled to extend the sum register dependent upon the contents of the carry-out counter. The extension occurs during addition of the most significant partial product to the sum of less significant partial products.