Patents by Inventor Choon Wei Khor

Choon Wei Khor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-level tracking of in-use state of cache lines
    Patent number: 9348591
    Abstract: This disclosure includes tracking of in-use states of cache lines to improve throughput of pipelines and thus increase performance of processors. Access data for a number of sets of instructions stored in an instruction cache may be tracked using an in-use array in a first array until the data for one or more of those sets reach a threshold condition. A second array may then be used as the in-use array to track the sets of instructions after a micro-operation is inserted into the pipeline. When the micro-operation retires from the pipeline, the first array may be cleared. The process may repeat after the second array reaches the threshold condition. During the tracking, an in-use state for an instruction line may be detected by inspecting a corresponding bit in each of the arrays. Additional arrays may also be used to track the in-use state.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: May 24, 2016
    Assignee: Intel Corporation
    Inventors: Ilhyun Kim, Chen Koren, Alexandre J. Farcy, Robert L. Hinton, Choon Wei Khor, Lihu Rappoport
  • Hiding instruction cache miss latency by running tag lookups ahead of the instruction accesses
    Patent number: 9158696
    Abstract: This disclosure provides techniques and apparatuses to enable early, run-ahead handling of IC and ITLB misses by decoupling the ITLB and IC tag lookups from the IC data (instruction bytes) accesses, and making ITLB and IC tag lookups run ahead of the IC data accesses.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: October 13, 2015
    Assignee: Intel Corporation
    Inventors: Ilhyun Kim, Alexandre J. Farcy, Choon Wei Khor, Robert L. Hinton
  • HIDING INSTRUCTION CACHE MISS LATENCY BY RUNNING TAG LOOKUPS AHEAD OF THE INSTRUCTION ACCESSES
    Publication number: 20140229677
    Abstract: This disclosure provides techniques and apparatuses to enable early, run-ahead handling of IC and ITLB misses by decoupling the ITLB and IC tag lookups from the IC data (instruction bytes) accesses, and making ITLB and IC tag lookups run ahead of the IC data accesses.
    Type: Application
    Filed: December 29, 2011
    Publication date: August 14, 2014
    Inventors: Ilhyun Kim, Alexandre J. Farcy, Choon Wei Khor, Robert L. Hinton
  • MULTI-LEVEL TRACKING OF IN-USE STATE OF CACHE LINES
    Publication number: 20130275733
    Abstract: This disclosure includes tracking of in-use states of cache lines to improve throughput of pipelines and thus increase performance of processors. Access data for a number of sets of instructions stored in an instruction cache may be tracked using an in-use array in a first array until the data for one or more of those sets reach a threshold condition. A second array may then be used as the in-use array to track the sets of instructions after a micro-operation is inserted into the pipeline. When the micro-operation retires from the pipeline, the first array may be cleared. The process may repeat after the second array reaches the threshold condition. During the tracking, an in-use state for an instruction line may be detected by inspecting a corresponding bit in each of the arrays. Additional arrays may also be used to track the in-use state.
    Type: Application
    Filed: December 29, 2011
    Publication date: October 17, 2013
    Inventors: Ilhyun Kim, Chen Koren, Alexandre J. Farcy, Robert L. Hinton, Choon Wei Khor, Lihu Rappoport