Patents by Inventor Choon Yong Ng
Choon Yong Ng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9515033Abstract: A monolithic microwave integrated circuit included a substrate, a first pad, a first line, a second line, a second pad, a third pad, a first active element, a second active element. The first line includes an input end connected to the first pad. The second line includes an input end connected to the first pad. The second and third pads are connected to the ground. The first active element includes a first gate electrode connected to the output end of the first line. The second active element includes a second gate electrode connected to the output end of the second line. The first pad is provided between the second pad and a third pad. Electrical length of the first line is equal to electrical length of the second line.Type: GrantFiled: March 2, 2016Date of Patent: December 6, 2016Assignee: Kabushiki Kaisha ToshibaInventor: Choon Yong Ng
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Publication number: 20160307856Abstract: A monolithic microwave integrated circuit included a substrate, a first pad, a first line, a second line, a second pad, a third pad, a first active element, a second active element. The first line includes an input end connected to the first pad. The second line includes an input end connected to the first pad. The second and third pads are connected to the ground. The first active element includes a first gate electrode connected to the output end of the first line. The second active element includes a second gate electrode connected to the output end of the second line. The first pad is provided between the second pad and a third pad. Electrical length of the first line is equal to electrical length of the second line.Type: ApplicationFiled: March 2, 2016Publication date: October 20, 2016Applicant: Kabushiki Kaisha ToshibaInventor: Choon Yong NG
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Patent number: 9347980Abstract: A radio frequency characteristics measurement jig device includes: a ground conductor part; a first coplanar line; a connection substrate; and a holding part. The first coplanar line includes a first dielectric layer, a first center conductive layer and first ground conductive layers. The connection substrate includes a second dielectric layer, a second center conductive layer, second ground conductive layers, and a third ground conductive layer. The holding part is configured to press the connection substrate to the first coplanar line and the signal terminal so as to allow electrical continuity between the first center conductive layer and the second center conductive layer on the first region, to allow electrical continuity between the first ground conductive layer and the second ground conductive layer, and to allow electrical continuity between the second center conductive layer on the second region and the signal terminal.Type: GrantFiled: July 3, 2014Date of Patent: May 24, 2016Assignee: Kabushiki Kaisha ToshibaInventor: Choon Yong Ng
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Publication number: 20150070044Abstract: A radio frequency characteristics measurement jig device includes: a ground conductor part; a first coplanar line; a connection substrate; and a holding part. The first coplanar line includes a first dielectric layer, a first center conductive layer and first ground conductive layers. The connection substrate includes a second dielectric layer, a second center conductive layer, second ground conductive layers, and a third ground conductive layer. The holding part is configured to press the connection substrate to the first coplanar line and the signal terminal so as to allow electrical continuity between the first center conductive layer and the second center conductive layer on the first region, to allow electrical continuity between the first ground conductive layer and the second ground conductive layer, and to allow electrical continuity between the second center conductive layer on the second region and the signal terminal.Type: ApplicationFiled: July 3, 2014Publication date: March 12, 2015Applicant: Kabushiki Kaisha ToshibaInventor: Choon Yong NG
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Patent number: 8710928Abstract: A semiconductor power amplifier of an embodiment includes: a plurality of unit FETs disposed in parallel in a direction of a substantially straight line connecting source electrodes of the unit FETs; a first via hole which connects the two source electrodes positioned between adjacent ones of the unit FETs in common and an RF ground electrode; and a second via hole which connects the source electrode on a side having no adjacent unit FET and the RF ground electrode. Each unit FET includes: a gate electrode which connects gate finger electrodes and leads out the gate finger electrodes; a drain electrode which connects drain finger electrodes disposed facing the gate finger electrodes and leads out the drain finger electrodes; and two source electrodes which connects source finger electrodes disposed facing the gate finger electrodes and lead out the source finger electrodes to opposing sides in a widthwise direction thereof.Type: GrantFiled: January 9, 2012Date of Patent: April 29, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Choon Yong Ng
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Patent number: 8610507Abstract: According to an embodiment, a power amplifier includes: an MMIC substrate; a high frequency probe pad disposed on the MMIC substrate; and a metal plate disposed on the MMIC substrate so as to adjoin to the high frequency probe pad, and connected to an MMIC external circuit via a bonding wire.Type: GrantFiled: December 20, 2011Date of Patent: December 17, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Choon Yong Ng, Kazutaka Takagi
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Patent number: 8427248Abstract: A stabilization network and a semiconductor device having the stabilization network wherein the stabilization network includes an active element having a negative resistance accompanying a high frequency negative resistance oscillation; and a tank circuit composed of a resistance connected to a main electrode of the active element, an inductance and capacitance which are connected in parallel with the resistance and synchronize with an oscillating frequency of the high frequency negative resistance oscillation, wherein the stabilization network is performed for suppressing a negative resistance accompanying a Gunn oscillation and obtaining stable and highly efficient power amplification.Type: GrantFiled: April 2, 2009Date of Patent: April 23, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Choon Yong Ng, Kazutaka Takagi, Naotaka Tomita
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Publication number: 20120319778Abstract: A semiconductor power amplifier of an embodiment includes: a plurality of unit FETs disposed in parallel in a direction of a substantially straight line connecting source electrodes of the unit FETs; a first via hole which connects the two source electrodes positioned between adjacent ones of the unit FETs in common and an RF ground electrode; and a second via hole which connects the source electrode on a side having no adjacent unit FET and the RF ground electrode. Each unit FET includes: a gate electrode which connects gate finger electrodes and leads out the gate finger electrodes; a drain electrode which connects drain finger electrodes disposed facing the gate finger electrodes and leads out the drain finger electrodes ; and two source electrodes which connects source finger electrodes disposed facing the gate finger electrodes and lead out the source finger electrodes to opposing sides in a widthwise direction thereof.Type: ApplicationFiled: January 9, 2012Publication date: December 20, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Choon Yong NG
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Publication number: 20120268211Abstract: According to an embodiment, a power amplifier includes: an MMIC substrate; a high frequency probe pad disposed on the MMIC substrate; and a metal plate disposed on the MMIC substrate so as to adjoin to the high frequency probe pad, and connected to an MMIC external circuit via a bonding wire.Type: ApplicationFiled: December 20, 2011Publication date: October 25, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Choon Yong Ng, Kazutaka Takagi
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Publication number: 20120049952Abstract: According to one embodiment, a wide band power amplifier is provided, which includes: a first amplifier unit that has a first center frequency; a second amplifier unit that is arranged in parallel to the first amplifier unit, and has a second center frequency higher than the first center frequency; a power divider connected to an input of the first amplifier unit and an input of the second amplifier unit; and a first power combiner connected to an output of the first amplifier unit and an output of the second amplifier unit.Type: ApplicationFiled: April 1, 2011Publication date: March 1, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Choon Yong NG
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Patent number: 8022769Abstract: According to one embodiment, there is a semiconductor device including a first active element, a second active element connected in parallel with the first active element, and a first stabilization circuit connected between a gate of the first active element and a gate of the second active element and configured with a parallel circuit of a gate bypass resistor, a gate bypass capacitor, and a gate bypass inductor, the first stabilization circuit having a resonant frequency equal to an odd mode resonant frequency.Type: GrantFiled: May 14, 2010Date of Patent: September 20, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Choon Yong Ng, Kazutaka Takagi, Naotaka Tomita
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Publication number: 20110018631Abstract: According to one embodiment, there is a semiconductor device including a first active element, a second active element connected in parallel with the first active element, and a first stabilization circuit connected between a gate of the first active element and a gate of the second active element and configured with a parallel circuit of a gate bypass resistor, a gate bypass capacitor, and a gate bypass inductor, the first stabilization circuit having a resonant frequency equal to an odd mode resonant frequency.Type: ApplicationFiled: May 14, 2010Publication date: January 27, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Choon Yong Ng, Kazutaka Takagi, Naotaka Tomita
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Publication number: 20100073099Abstract: A stabilization network and a semiconductor device having the stabilization network wherein the stabilization network includes an active element having a negative resistance accompanying a high frequency negative resistance oscillation; and a tank circuit composed of a resistance connected to a main electrode of the active element, an inductance and capacitance which are connected in parallel with the resistance and synchronize with an oscillating frequency of the high frequency negative resistance oscillation, wherein the stabilization network is performed for suppressing a negative resistance accompanying a Gunn oscillation and obtaining stable and highly efficient power amplification.Type: ApplicationFiled: April 2, 2009Publication date: March 25, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Choon Yong NG, Kazutaka Takagi, Naotaka Tomita
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Patent number: 7521981Abstract: A mixer circuit. The mixer circuit comprises a double-balanced mixer and a carrier-leakage calibration cell. The double-balanced mixer has first and second input pairs whereby the first input pair receives the first differential input signal. The carrier-leakage calibration cell receives the second differential input signal and a differential calibration current and generates first and second output voltages to the second input pair of the double-balanced mixer.Type: GrantFiled: June 11, 2007Date of Patent: April 21, 2009Assignee: Mediatek Singapore Pte LtdInventors: Choon Yong Ng, Ee Sze Khoo
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Publication number: 20080303579Abstract: A mixer circuit. The mixer circuit comprises a double-balanced mixer and a carrier-leakage calibration cell. The double-balanced mixer has first and second input pairs whereby the first input pair receives the first differential input signal. The carrier-leakage calibration cell receives the second differential input signal and a differential calibration current and generates first and second output voltages to the second input pair of the double-balanced mixer.Type: ApplicationFiled: June 11, 2007Publication date: December 11, 2008Applicant: MEDIATEK SINGAPORE PTE LTDInventors: Choon Yong NG, Ee Sze Khoo