Patents by Inventor Choong Chee

Choong Chee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080017976
    Abstract: A method of packaging a die includes attaching the die to a substrate; underfilling the space between the die and the substrate with a first material, and placing a second material in contact with at least a portion of the die and the substrate after underfilling the space between the die and substrate with the first material. A system includes a semiconductor package having a substrate, a die attached to the substrate, an underfill material positioned between the die and the substrate, and a molding material in contact with at least a portion of the substrate and the die. A heat sink is also in thermal contact with the semiconductor package.
    Type: Application
    Filed: August 8, 2007
    Publication date: January 24, 2008
    Inventors: Yin Lai, Choong Chee, Edward Then, Cheong Ng, Mun Low
  • Publication number: 20070133081
    Abstract: According to embodiments of the present invention, a first layer of electrically conductive material may be disposed in a recess in a micro-electromechanical system (MEMS) base. An electrically charged gel network may be disposed in the recess on the first layer of electrically conductive material. A second layer of electrically conductive material may be disposed in the recess on the cross-linked co-polymer gel network. A functionalizer may be disposed on the first and the second layers of electrically conductive material.
    Type: Application
    Filed: February 6, 2007
    Publication date: June 14, 2007
    Inventor: Choong Chee
  • Publication number: 20060214311
    Abstract: A method of packaging a die includes attaching the die to a substrate; underfilling the space between the die and the substrate with a first material, and placing a second material in contact with at least a portion of the die and the substrate after underfilling the space between the die and substrate with the first material. A system includes a semiconductor package having a substrate, a die attached to the substrate, an underfill material positioned between the die and the substrate, and a molding material in contact with at least a portion of the substrate and the die. A heat sink is also in thermal contact with the semiconductor package.
    Type: Application
    Filed: September 30, 2003
    Publication date: September 28, 2006
    Inventors: Yin Lai, Choong Chee, Edward Then, Cheong Ng, Mun Low
  • Publication number: 20050264903
    Abstract: According to embodiments of the present invention, a first layer of electrically conductive material may be disposed in a recess in a micro-electromechanical system (MEMS) base. An electrically charged gel network may be disposed in the recess on the first layer of electrically conductive material. A second layer of electrically conductive material may be disposed in the recess on the cross-linked co-polymer gel network. A functionalizer may be disposed on the first and the second layers of electrically conductive material.
    Type: Application
    Filed: June 1, 2004
    Publication date: December 1, 2005
    Inventor: Choong Chee
  • Publication number: 20050221532
    Abstract: A stress-compensation layer is formed by pressing a solder bump into a compressible film within a mold chase. The stress-compensation layer flows against the solder bump and the compressible film such that at least a portion of the solder ball is embedded in the stress-compensation layer. The compressible film is removed to reveal at least a portion of the solder bump exposed and free of the stress-compensation layer. An article that exhibits a stress-compensation layer with a surface characteristic of the imposed flexible film is also included. A computing system that includes a stress-compensation layer with a surface characteristic of the imposed flexible film is also included.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 6, 2005
    Inventor: Choong Chee
  • Publication number: 20050133938
    Abstract: A system for chip packaging includes an adamantoid packaging composition. The adamantoid composition ameliorates the CTE mismatch that typically exists between a packaged die and a resin-impregnated fiberglass mounting substrate. In an embodiment, the system includes a packaging composition that alone exhibits a CTE that is characteristic of an inorganic-filled underfill composite previously known. An embodiment is also directed to the assembly of a chip package that uses an adamantoid packaging composition.
    Type: Application
    Filed: December 18, 2003
    Publication date: June 23, 2005
    Inventors: Sheau Lim, Choong Chee