Patents by Inventor ChoongHwan Kwon

ChoongHwan Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9318403
    Abstract: An integrated circuit packaging system including: connecting a first integrated circuit device and a package substrate; attaching a support bump to the package substrate; providing a second integrated circuit device having an inner encapsulation; applying a magnetic film on the inner encapsulation of the second integrated circuit device; and mounting the second integrated circuit device over the first integrated circuit device with the magnetic film on the first integrated circuit device and the support bump.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: April 19, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Sung Soo Kim, DongSik Kim, ChoongHwan Kwon
  • Publication number: 20110298106
    Abstract: An integrated circuit packaging system including: connecting a first integrated circuit device and a package substrate; attaching a support bump to the package substrate; providing a second integrated circuit device having an inner encapsulation; applying a magnetic film on the inner encapsulation of the second integrated circuit device; and mounting the second integrated circuit device over the first integrated circuit device with the magnetic film on the first integrated circuit device and the support bump.
    Type: Application
    Filed: August 16, 2011
    Publication date: December 8, 2011
    Inventors: Sung Soo Kim, DongSik Kim, ChoongHwan Kwon
  • Publication number: 20100237500
    Abstract: A semiconductor substrate includes a first conductive layer formed over the semiconductor substrate. The first conductive layer has first and second portions which are electrically isolated during formation of the first conductive layer. A solder resist layer is formed over the first conductive layer and semiconductor substrate. An opening is formed in the solder resist layer to expose the first conductive layer. A seed layer is formed over the semiconductor substrate and first conductive layer within the opening. A second conductive layer is formed over the seed layer within the opening. The opening may expose the second portion of the first conductive layer due to solder resist registration shifting causing a defect condition. The second conductive layer electrically contacts the first and second portions of the first conductive layer. By testing the first and second portions of the first conductive layer, the defect condition can be identified.
    Type: Application
    Filed: March 20, 2009
    Publication date: September 23, 2010
    Applicant: STATS CHIPPAC, LTD.
    Inventors: ChoongHwan Kwon, SooMoon Park, HeeJo Chi
  • Publication number: 20080315374
    Abstract: An integrated circuit package-in-package system comprising: connecting a first integrated circuit device and a package substrate; applying a magnetic film over the first integrated circuit device; mounting a second integrated circuit device having an inner encapsulation over the magnetic film; and forming a package encapsulation over the first integrated circuit device, the magnetic film, and the second integrated circuit device.
    Type: Application
    Filed: June 25, 2007
    Publication date: December 25, 2008
    Inventors: Sung Soo Kim, DongSik Kim, ChoongHwan Kwon