Patents by Inventor Choong-Hyun Lee

Choong-Hyun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250105471
    Abstract: A secondary battery includes: an electrode assembly including a first electrode plate, a second electrode plate, and a separator; a case accommodating the electrode assembly and having an opening; a cap plate coupled to and sealing the opening in the case; a first terminal plate on the cap plate and electrically connected to the first electrode plate; and a first current collector plate between the first terminal plate and the electrode assembly to electrically connect the first terminal plate to the electrode assembly. The first current collector plate has a first protrusion that passes through the cap plate and is connected to the first terminal plate.
    Type: Application
    Filed: March 15, 2024
    Publication date: March 27, 2025
    Inventors: Tae Jun KIM, Jae Hyun YOO, Choong Hoon LEE, Gi Jang AHN
  • Patent number: 12260606
    Abstract: An apparatus for detecting a mark by using image matching includes a damaged content obtaining unit configured to obtain damaged content generated based on original content including a plurality of cuts; a pre-processed content generating unit configured to generate pre-processed content by merging one or more images included in the damaged content or removing a partial region of one or more cuts included in the damaged content; a matchable content generating unit configured to generate matchable content, in which sizes or locations of one or more cuts included in the pre-processed content are adjusted by comparing one or more cuts included in the original image and the one or more cuts included in the pre-processed content; a matching unit configured to compare the original content with the matchable content, for each cut.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: March 25, 2025
    Assignee: NAVER WEBTOON LTD.
    Inventors: Sang Min Park, Choong Hyun Seo, Jin Seo Lee, Seung Ik Kim, Yo Seob Lee
  • Patent number: 12255019
    Abstract: A multilayer electronic component includes: a body including a capacitance forming portion in which dielectric layers and internal electrodes are alternately disposed in a first direction, and cover portions disposed on an upper surface and a lower surface of the capacitance forming portion, respectively, in the first direction; and external electrodes disposed on the body, wherein the cover portion includes a plurality of dielectric grains and a plurality of pores, and Gn/Pn is more than 10 and less than 30, in which Gn is the number of dielectric grains included in the cover portion and Pn is the number of pores included in the cover portion.
    Type: Grant
    Filed: April 11, 2024
    Date of Patent: March 18, 2025
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jin Bok Shin, Yu Ra Shin, Seung Yong Lee, Jung Hyun An, Yong Hwa Lee, Da Hyeon Go, Choong Seop Jeon, Min Soo Kim
  • Publication number: 20250081851
    Abstract: A thermal image sensor and a method of manufacturing the same. The thermal image sensor includes: a substrate; a row electrode and a column electrode on the substrate; a multi-layer stack including an absorption layer and a temperature sensor; supporting arms that extend from diagonal corners of the multi-layer stack and that are spaced apart from both sides of the multi-layer stack, wherein the supporting arms have a concave-convex shape including a plurality of concave portions and a plurality of convex portions; and legs protruding from the row electrode and the column electrode, wherein the legs are connected to extended ends of the supporting arms to allow the multi-layer stack to float above the substrate.
    Type: Application
    Filed: December 6, 2023
    Publication date: March 6, 2025
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Choong Ho RHEE, Jae Chul PARK, Byong Gwon SONG, Jang Woo YOU, Yong Seop YOON, Du Hyun LEE
  • Publication number: 20240357799
    Abstract: There is provided a semiconductor memory device capable of improving performance and reliability of an element. The semiconductor memory device includes a substrate including a cell region and a peripheral region, a cell region isolation layer in the substrate, isolating the cell region from the peripheral region, an isolation active region surrounded by the cell region isolation layer, a bit line structure on the cell region, including a cell conductive line and a cell gate electrode in the substrate of the cell region, crossing the cell conductive line.
    Type: Application
    Filed: November 14, 2023
    Publication date: October 24, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Choong Hyun LEE, Joon Cheol KIM, Kang-Uk KIM, Jin A KIM, Byoung Wook JANG, Young-Seung CHO
  • Publication number: 20240303476
    Abstract: A neural network system includes a neural network circuit including first memory cells arranged in an array; and a self-referencing circuit electrically connected to a row line or a column line of the neural network circuit and configured to apply current to the connected row line or column line so that a plurality of target memory cells have preset target weights, wherein the target memory cells include all memory cells positioned on the row line or the column line to which the self-referencing circuit is connected.
    Type: Application
    Filed: March 6, 2024
    Publication date: September 12, 2024
    Applicant: PEBBLE SQUARE, INC.
    Inventor: Choong Hyun LEE
  • Publication number: 20240107751
    Abstract: A semiconductor memory device is provided. The semiconductor memory device comprises a substrate including a cell region having an active region defined by a cell element isolation layer, a peripheral region near the cell region, and a boundary region between the cell region and the peripheral region. The device includes a word line structure in the substrate and extending in a first direction, a bit line structure on the substrate extending from the cell region to the boundary region in a second direction that crosses the first direction, including first and second cell conductive layers sequentially stacked on the substrate, and a bit line contact between the substrate and the bit line structure and connecting the substrate with the bit line structure. The second cell conductive layer in the boundary region is thicker than the second cell conductive layer in the cell region.
    Type: Application
    Filed: July 14, 2023
    Publication date: March 28, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jin A KIM, Kang-Uk KIM, Sang Hoon MIN, Choong Hyun LEE
  • Publication number: 20240052488
    Abstract: Provided is a feeding block for transferring a process gas to a process chamber, the feeding block including a body, a first annular channel provided in the body, at least one first supply channel extending from an outer surface of the body to the first annular channel to supply a first process gas to the first annular channel, and at least one first discharge channel extending from the first annular channel to an outer surface of the body to discharge the first process gas in the first annular channel to an outside, wherein the body is provided as a single member such that the first supply channel, the first annular channel, and the first discharge channel have continuous inner surfaces.
    Type: Application
    Filed: August 9, 2023
    Publication date: February 15, 2024
    Applicant: WONIK IPS CO., LTD.
    Inventors: Choong Hyun LEE, Chong Hwan JONG, Dong Bum KANG
  • Patent number: 11804371
    Abstract: Provided is a substrate treatment apparatus including a treatment container equipped with a conductive member. The conductive member is made of a material having a lower resistivity than that of the treatment container. The conductive member prevents a rise of an electric potential of the treatment container, which is caused by charging during treatment of a substrate, thereby preventing the substrate from being contaminated and damaged by particles and electrostatic arcing.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: October 31, 2023
    Assignee: SEMES CO., LTD.
    Inventors: Do Yeon Kim, Se Hoon Oh, Won Geun Kim, Ju Mi Lee, Ho Jong Hwang, Pil Kyun Heo, Hyun Yoon, Choong Hyun Lee, Hyun Goo Park
  • Publication number: 20220157644
    Abstract: A substrate supporting assembly includes a susceptor plate including at least one substrate seat, and a plurality of gas flow lines for supplying a lifting gas, an acceleration gas, and a deceleration gas to the substrate seat, and at least one satellite on the at least one substrate seat and including an upper surface, and a lower surface where a rotation pattern for receiving a rotational force and a braking force from the acceleration gas and the deceleration gas is provided. The at least one satellite is lifted from the at least one substrate seat by the lifting gas supplied from the at least one substrate seat, is rotated relative to the susceptor plate by the acceleration gas supplied in a forward direction of rotation, to rotate the substrate, and is decelerated or stopped by the deceleration gas supplied in a reverse direction of rotation.
    Type: Application
    Filed: November 5, 2021
    Publication date: May 19, 2022
    Applicant: WONIK IPS CO., LTD.
    Inventors: Hyun Jong LEE, Chong Hwan JONG, Ho Jin NAM, Choong hyun LEE, Eo jin KWON
  • Publication number: 20210013029
    Abstract: Provided is a substrate treatment apparatus including a treatment container equipped with a conductive member. The conductive member is made of a material having a lower resistivity than that of the treatment container. The conductive member prevents a rise of an electric potential of the treatment container, which is caused by charging during treatment of a substrate, thereby preventing the substrate from being contaminated and damaged by particles and electrostatic arcing.
    Type: Application
    Filed: July 2, 2020
    Publication date: January 14, 2021
    Applicant: SEMES CO., LTD.
    Inventors: Do Yeon KIM, Se Hoon OH, Won Geun KIM, Ju Mi LEE, Ho Jong HWANG, Pil Kyun HEO, Hyun YOON, Choong Hyun LEE, Hyun Goo PARK
  • Patent number: 10109710
    Abstract: A semiconductor device having a channel region that is formed in a germanium layer and has a first conductive type, and a source region and a drain region that are formed in the germanium layer and have a second conductive type different from the first conductive type, wherein an oxygen concentration in the channel region is less than an oxygen concentration in a junction interface between at least one of the source region and the drain region and a region that surrounds the at least one of the source region and the drain region and has the first conductive type.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: October 23, 2018
    Assignee: Japan Science and Technology Agency
    Inventors: Akira Toriumi, Choong-hyun Lee, Tomonori Nishimura
  • Publication number: 20180016194
    Abstract: Disclosed is a method for producing a carbide derived carbon layer with a dimple pattern. The method includes forming a dimple pattern on the surface of a carbide ceramic material and forming a carbide derived carbon layer thereon. Also disclosed is a carbide derived carbon layer with a dimple pattern produced by the method. The carbide derived carbon layer with dimple pattern has high wear resistance, good adhesion to a machine part, and excellent frictional characteristics. The carbide derived carbon layer can be applied to various fields, such as coating of carbide coated and carbide materials. Particularly, the carbide derived carbon layer is suitable for coating of machine parts (e.g., sliding parts, mechanical seals, piston rings, and compressor vanes) where excellent mechanical properties are needed.
    Type: Application
    Filed: June 29, 2017
    Publication date: January 18, 2018
    Applicant: Korea University Research and Business Foundation
    Inventors: Dae-Soon Lim, Eung-Seok Lee, Tae Hyun Kim, Choong Hyun Lee, Young Kyun Lim
  • Publication number: 20170317170
    Abstract: A semiconductor device having a channel region that is formed in a germanium layer and has a first conductive type, and a source region and a drain region that are formed in the germanium layer and have a second conductive type different from the first conductive type, wherein an oxygen concentration in the channel region is less than an oxygen concentration in a junction interface between at least one of the source region and the drain region and a region that surrounds the at least one of the source region and the drain region and has the first conductive type.
    Type: Application
    Filed: November 2, 2015
    Publication date: November 2, 2017
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Akira TORIUMI, Choong-hyun LEE, Tomonori NISHIMURA
  • Patent number: 9722026
    Abstract: A semiconductor structure includes: a germanium layer; and a first insulating film that is formed on an upper surface of the germanium layer, primarily contains germanium oxide and a substance having an oxygen potential lower than an oxygen potential of germanium oxide, and has a physical film thickness of 3 nm or less; wherein a half width of frequency to height in a 1 ?m square area of the upper surface of the germanium layer is 0.7 nm or less.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: August 1, 2017
    Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Akira Toriumi, Toshiyuki Tabata, Choong Hyun Lee, Tomonori Nishimura, Cimang Lu
  • Patent number: 9691620
    Abstract: A semiconductor structure includes: a germanium layer 30; and an insulating film that has a film 32 that includes a germanium oxide and is formed on the germanium layer and a high dielectric oxide film 34 that is formed on the film including the germanium oxide and has a dielectric constant higher than that of a silicon oxide, wherein: an EOT of the insulating film is 2 nm or less; and on a presumption that an Au acting as a metal film is formed on the insulating film, a leak current density is 10?5×EOT+4 A/cm2 or less in a case where a voltage of the metal film with respect to the germanium layer is applied from a flat band voltage to an accumulation region side by 1 V.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: June 27, 2017
    Assignee: Japan Science and Technology Agency
    Inventors: Akira Toriumi, Choong-hyun Lee
  • Patent number: 9647074
    Abstract: A method of manufacturing a semiconductor substrate includes: heat-treating a germanium layer 30 with an oxygen concentration of 1×1016 cm?3 or greater in a reducing gas atmosphere at 700° C. or greater. Alternatively, a method of manufacturing a semiconductor substrate includes heat-treating a germanium layer 30 having an oxygen concentration of 1×1016 cm?3 or greater in a reducing gas atmosphere so that the oxygen concentration decreases.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: May 9, 2017
    Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Akira Toriumi, Choong-hyun Lee, Tomonori Nishimura
  • Publication number: 20160276445
    Abstract: A method of manufacturing a semiconductor substrate includes: heat-treating a germanium layer 30 with an oxygen concentration of 1×1016 cm?3 or greater in a reducing gas atmosphere at 700° C. or greater. Alternatively, a method of manufacturing a semiconductor substrate includes heat-treating a germanium layer 30 having an oxygen concentration of 1×1016 cm?3 or greater in a reducing gas atmosphere so that the oxygen concentration decreases.
    Type: Application
    Filed: October 10, 2014
    Publication date: September 22, 2016
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Akira TORIUMI, Choong-hyun LEE, Tomonori NISHIMURA
  • Publication number: 20160218182
    Abstract: A semiconductor structure includes: a germanium layer; and a first insulating film that is formed on an upper surface of the germanium layer, primarily contains germanium oxide and a substance having an oxygen potential lower than an oxygen potential of germanium oxide, and has a physical film thickness of 3 nm or less; wherein a half width of frequency to height in a 1 ?m square area of the upper surface of the germanium layer is 0.7 nm or less.
    Type: Application
    Filed: June 6, 2014
    Publication date: July 28, 2016
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Akira TORIUMI, Toshiyuki TABATA, Choong Hyun LEE, Tomonori NISHIMURA, Cimang LU
  • Publication number: 20160081620
    Abstract: An apparatus includes: a receiving unit for receiving a sensor signal for a body of a user from a wearable apparatus; a controller for classifying a physical activity of the user as one of a plurality of predefined activity models based on the received sensor signal, and generating prediction information about the body of the user based on a result of the classifying and profile information about the user; and an output device for outputting health care information to the user based on the prediction information.
    Type: Application
    Filed: September 18, 2015
    Publication date: March 24, 2016
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Rangavittal NARAYANAN, Vijay Narayan TIWARI, Saswata SAHOO, Mithun Manjnath NAYAK, Shankar M. VENKATESAN, Aloknath DE, Vivek JILLA, Choong-hyun LEE, Subramanian RAMAKRISHNAN, Ramachandran NARASIMHAMURTHY, Avinash PRASAD