Abstract: A vehicle assist handle is formed so that a guide block is mounted on a surface of a headliner on which the assist handle is mounted and which is fixedly fitted into or separated from the guide block in a sliding manner to be used for other purposes by separating the assist handle from the surface of the headliner. The vehicle assist handle may be pushed in a direction parallel to the surface of the headliner to be assembled or separated when slidably guided to the guide block. The guide block can support a weight of an occupant applied to the assist handle. The vehicle assist handle can be used safely and conveniently. In addition, as a sunglass case, a storage case, or a rack may be fixedly coupled to the guide block in the sliding manner.

Abstract: Disclosed is a method for transient liquid-phase bonding between metal materials using a magnetic force. In particular, in the method, a magnetic force is applied to a transient liquid-phase bonding process, thereby shortening a transient liquid-phase bonding time between the metal materials, and obtaining high bonding strength. To this end, an attractive magnetic force is applied to a ferromagnetic base while a repulsive magnetic force is applied to a diamagnetic base, thereby to accelerate diffusion. This may reduce a bonding time during a transient liquid-phase bonding process between two bases and suppress formation of Kirkendall voids and voids and suppress a layered structure of an intermetallic compound, thereby to increase a bonding strength.

Abstract: Disclosed is a method for transient liquid-phase bonding between metal materials using a magnetic force. In particular, in the method, a magnetic force is applied to a transient liquid-phase bonding process, thereby shortening a transient liquid-phase bonding time between the metal materials, and obtaining high bonding strength. To this end, an attractive magnetic force is applied to a ferromagnetic base while a repulsive magnetic force is applied to a diamagnetic base, thereby to accelerate diffusion. This may reduce a bonding time during a transient liquid-phase bonding process between two bases and suppress formation of Kirkendall voids and voids and suppress a layered structure of an intermetallic compound, thereby to increase a bonding strength.

Abstract: A semiconductor device includes a memory cell array, which further includes an array of first magnetic memory cells and an array of second magnetic memory cells. Each of the first magnetic memory cells includes a first magnetic tunnel junction structure having a reversible resistance state, and each of the second magnetic memory cells includes a second magnetic tunnel junction structure having a one-time programmable (OTP) resistance state.

Abstract: A semiconductor device includes a memory cell array, which further includes an array of first magnetic memory cells and an array of second magnetic memory cells. Each of the first magnetic memory cells includes a first magnetic tunnel junction structure having a reversible resistance state, and each of the second magnetic memory cells includes a second magnetic tunnel junction structure having a one-time programmable (OTP) resistance state.

Abstract: A semiconductor device includes a memory cell array, which further includes an array of first magnetic memory cells and an array of second magnetic memory cells. Each of the first magnetic memory cells includes a first magnetic tunnel junction structure having a reversible resistance state, and each of the second magnetic memory cells includes a second magnetic tunnel junction structure having a one-time programmable (OTP) resistance state.

Abstract: An image sensor includes a first semiconductor layer having a first semiconductor region and a first insulating region, and a second semiconductor layer under the first semiconductor layer including a second semiconductor region and a second insulating region. The first semiconductor layer includes a first transistor having first source or drain regions in the first semiconductor region and a first gate electrode in the first insulating region, a contact wiring, a first wiring layer electrically connecting the contact wiring and the first transistor, and a first junction region electrically connected to the first wiring layer. The second semiconductor layer includes a second transistor having second source or drain regions in the second semiconductor region and a second gate electrode in the second insulating region, a second wiring layer electrically connecting the contact wiring and the second transistor, and a second junction region electrically connected to the second wiring layer.

Abstract: An image sensor includes a first semiconductor layer having a first semiconductor region and a first insulating region, and a second semiconductor layer under the first semiconductor layer including a second semiconductor region and a second insulating region. The first semiconductor layer includes a first transistor having first source or drain regions in the first semiconductor region and a first gate electrode in the first insulating region, a contact wiring, a first wiring layer electrically connecting the contact wiring and the first transistor, and a first junction region electrically connected to the first wiring layer. The second semiconductor layer includes a second transistor having second source or drain regions in the second semiconductor region and a second gate electrode in the second insulating region, a second wiring layer electrically connecting the contact wiring and the second transistor, and a second junction region electrically connected to the second wiring layer.

Abstract: A resistive-type memory device is disclosed. The resistive-type memory device includes a memory cell array and a control logic circuit. The control logic circuit accesses the memory cell array in response to a command and an address provided from an outside. The memory cell array includes at least a first group of resistive-type memory cells and a second group of resistive-type memory cells. Each of the first group of resistive-type memory cells has a first feature size and each of the second group of resistive-type memory cells has a second feature size that is different from the first feature size.

Abstract: Magnetic random access memory (MRAM)-based frame buffering apparatus are provided that may reduce a size and power consumption thereof by using a pixel self-refresh (PSR) method. The MRAM-based frame buffering apparatus includes a frame buffer memory including magnetic random access memory (MRAM). The frame buffer memory stores at least one piece of frame data. The MRAM-based frame buffering apparatus further includes a magnetic field sensor configured to detect an external magnetic field; and a frame buffer controller configured to control the storing of the at least one piece of frame data according to the intensity of the detected external magnetic field.

Abstract: A semiconductor device comprises a magneto-resistive device capable of performing multiple functions with low power. The semiconductor device comprises a cell transistor in which a first impurity region and a second impurity region are respectively arranged on both sides of a channel region in a channel direction, a source line connected to the first impurity region of the cell transistor, and the magneto-resistive device connected to the second impurity region of the cell transistor. The first impurity region and the second impurity region are asymmetrical about a center of the cell transistor in the channel direction with respect to at least one of a shape and an impurity concentration distribution.

Abstract: A memory cell includes a metal oxide semiconductor (MOS) capacitor including a gate coupled to a storage node and an electrode coupled to a synchronization control line. The MOS capacitor adds a coupling voltage to the gate based on a change in voltage on the synchronization control line. The coupling voltage may maintain the storage node within a predetermined range.

Abstract: Magnetic random access memory (MRAM)-based frame buffering apparatus are provided that may reduce a size and power consumption thereof by using a pixel self-refresh (PSR) method. The MRAM-based frame buffering apparatus includes a frame buffer memory including magnetic random access memory (MRAM). The frame buffer memory stores at least one piece of frame data. The MRAM-based frame buffering apparatus further includes a magnetic field sensor configured to detect an external magnetic field; and a frame buffer controller configured to control the storing of the at least one piece of frame data according to the intensity of the detected external magnetic field.

Abstract: A semiconductor device comprises a magneto-resistive device capable of performing multiple functions with low power. The semiconductor device comprises a cell transistor in which a first impurity region and a second impurity region are respectively arranged on both sides of a channel region in a channel direction, a source line connected to the first impurity region of the cell transistor, and the magneto-resistive device connected to the second impurity region of the cell transistor. The first impurity region and the second impurity region are asymmetrical about a center of the cell transistor in the channel direction with respect to at least one of a shape and an impurity concentration distribution.

Abstract: A magnetic memory device includes first and second magnetic memory cells coupled to first and second bit lines, respectively. The first and second magnetic memory cells respectively include a pinned magnetic layer, a free magnetic layer, and a tunnel insulating layer therebetween. Respective stacking orders of the pinned magnetic layer, the tunnel insulating layer, and the free magnetic layer are different in the first and second magnetic memory cells. The magnetic memory device further includes at least one transistor that is configured to couple the first and second magnetic memory cells to a common source line. Related methods of operation are also discussed.

Abstract: A magnetic memory device includes word lines, bit lines intersecting the word lines, magnetic memory elements disposed at intersections between the word lines and the bit lines, and selection transistors connected to the word lines. The magnetic memory elements share a word line among the plurality of word lines and also share a selection transistor connected to the word line that is shared among the selection transistors. Related systems and operating methods are also described.

Abstract: A display driving circuit includes a frame buffer that stores a plurality of pieces of line data, and a buffer controller. The buffer controller receives a data packet, and outputs first line data included in the data packet or second line data stored in the frame buffer as grayscale data based on flag information included in the data packet.

Abstract: A magnetic memory device includes first and second magnetic memory cells coupled to first and second bit lines, respectively. The first and second magnetic memory cells respectively include a pinned magnetic layer, a free magnetic layer, and a tunnel insulating layer therebetween. Respective stacking orders of the pinned magnetic layer, the tunnel insulating layer, and the free magnetic layer are different in the first and second magnetic memory cells. The magnetic memory device further includes at least one transistor that is configured to couple the first and second magnetic memory cells to a common source line. Related methods of operation are also discussed.

Abstract: A magnetic memory device includes word lines, bit lines intersecting the word lines, magnetic memory elements disposed at intersections between the word lines and the bit lines, and selection transistors connected to the word lines. The magnetic memory elements share a word line among the plurality of word lines and also share a selection transistor connected to the word line that is shared among the selection transistors. Related systems and operating methods are also described.

Abstract: Disclosed herein is a micro-electrode array package including a micro-electrode array comprising: a substrate section including a liquid crystal polymer; an electrode section collecting and transferring bio-signals; and a cover section insulating and protecting the electrode section and including a liquid crystal polymer, wherein the electrode section is disposed in contact with one surface of the substrate section, the cover section is adhered in contact with the surface of the substrate section on which the electrode section is disposed, and a space independent from the external environment is formed between the substrate section and the cover section adhered thereto.