Abstract: Determining a semiconductor device manufacturing parameter may include determining an EPM (electrical measurement parameters) group that has a correlation in a baseline EPM dataset including EPMs of a device manufactured under a baseline condition, deriving principal components (PCs) corresponding to main correlation axes between EPMs in the EPM group, deriving a PC-based dataset including a baseline PC dataset and a conditional split PC dataset by converting the baseline EPM dataset and a conditional split EPM dataset measured from devices manufactured under conditional splits into a PC domain, determining, using the PC-based dataset, respective PCs which are effectively changed by the conditional splits, obtaining split variation information of the conditional splits, extracting an optimal point capable of optimizing a figure of merit of a semiconductor device within a range of the PC-based dataset, and deriving information for process feedback for realizing the optimal point using the split variation infor

Abstract: Disclosed are a support beam structure capable of extending a span and reducing a height of a ceiling structure and an installing method thereof. The support beam structure includes an H-beam extending in a longitudinal direction, an inclined extension part fastened to a lower surface or a side surface of the H-beam and inclined in such a way as to flare at an upper end thereof, a reinforcing part for reinforcing the inclined extension part, a deck placed on an upper end of the inclined extension part, and a concrete layer for filling a top of the inclined extension part, a top of the H-beam, and a top of the deck.

Abstract: Disclosed are a support beam structure capable of extending a span and reducing a height of a ceiling structure and an installing method thereof. The support beam structure includes an H-beam extending in a longitudinal direction, an inclined extension part fastened to a lower surface or a side surface of the H-beam and inclined in such a way as to flare at an upper end thereof, a reinforcing part for reinforcing the inclined extension part, a deck placed on an upper end of the inclined extension part, and a concrete layer for filling a top of the inclined extension part, a top of the H-beam, and a top of the deck.

Abstract: Disclosed are a support beam structure capable of extending a span and reducing a height of a ceiling structure and an installing method thereof. The support beam structure includes an H-beam extending in a longitudinal direction, an inclined extension part fastened to a lower surface or a side surface of the H-beam and inclined in such a way as to flare at an upper end thereof, a reinforcing part for reinforcing the inclined extension part, a deck placed on an upper end of the inclined extension part, and a concrete layer for filling a top of the inclined extension part, a top of the H-beam, and a top of the deck.

Abstract: A mobile phone payment method and system in which a mobile phone, a photo receiver, and a control server for storing payment-related information of a user of the mobile phone, download the payment-related information of the user from the control server to the mobile phone. The payment-related information is converted into binary code data. A light signal from a backlight of the mobile phone, based on the binary code data, is transmitted to the photo receiver. The photo receiver authenticates the binary data from the received light signal and authorizes payment accordingly.

Abstract: Disclosed are a three dimensional metal device floated over a semiconductor substrate, a circuit thereof, and a manufacturing method thereof. A passive electric device for wireless communications and optical communications, such as a spiral inductor, a solenoid inductor, a spiral transformer, a solenoid transformer, a micro mirror, a transmission line is floated over and apart by a few ten micrometers from the semiconductor substrate. These three dimensional metal devices remarkably decrease a signal loss to the substrate, to thereby enhance the device performance, to allow a modeling of a device separated from the substrate, and to make it possible to form an integrated circuit below the device. Further, the three dimensional metal device is manufactured in a monolithic method on the integrated circuit such that it does not affect on the integrated circuit formed therebelow.

Abstract: A method for manufacturing a semiconductor device where a passive element, such as, an inductor, is floating over a substrate, where an integrated circuit is formed, such that the overall area of the semiconductor device may be highly reduced. According to the present invention, a first metal layer is formed on the substrate, a first masking layer is formed on a portion of the first metal layer, a second metal layer is formed on other portion of the first metal layer on which the first masking layer is not formed, and a second masking layer is formed on the first masking layer and the second metal layer. Then, the first masking layer and a portion of the second masking layer which includes a portion which covers the first masking layer is removed, a third metal layer is formed on portions of the first and second metal layers which are exposed by the step of removing the first masking layer and the portion of the second masking layer.

Abstract: Disclosed is an ink jet print head and a method of producing the same, the ink jet print head including a plurality of ink ejecting orifices which are formed with a desired shape and a uniform size by only once using metal plating technique, having an excellent productivity and a low manufacturing cost. According to a first embodiment of the present invention, in the steps for forming an improved metal barrier layer, which is comprised of the conventional barrier layer and the conventional nozzle plate combined together, the metal barrier layer can be formed on a wetting layer by using electrolytic plating or electroless plating of Ni. As a result, an upper surface of a first photoresist mold is completely covered with the overflowing Ni. Further, an upper portion of a second photoresist mold is partially covered with the overplating Ni and is partially opened at a proper size and a desired shape. Thereby, an ink ejecting orifice is created at the upper portion of the second photoresist mold.

Abstract: A structure and the fabrication method of two-color IR detector are disclosed. Disclosed two-color IR detector structure is a n-p-N structure which can be realized using only two-layer HgCdTe. The most important factor in the two-color IR detector structure is the formation of the potential barrier in the conduction band of p-N heterojunction. This potential barrier prevents photogenerated minority carriers in p-HgCdTe region from diffusing to and being collected by N-HgCdTe region (larger band gap diode). The calculated potential barrier heights under the thermal equilibrium at 77 K are 21 kT (141 meV) and 13.4 kT (89 meV) for the cases of p-Hg.sub.0.78 Cd.sub.0.22 Te/N-Hg.sub.0.69 Cd.sub.0.3l Te and p-Hg.sub.0.69 Cd.sub.0.31 Te/N-Hg.sub.0.636 Cd.sub.0.364 Te with each side carrier concentration of 5.times.10.sup.15 and 1.times.10.sub.16 cm.sup.-3, respectively.

Abstract: A heat generating type ink-jet print head including an ink supply passage for receiving an ink from an ink container, a micro chamber for storing the ink and nozzles, all being directly formed on a substrate, and a method for fabricating the ink-jet print head using an electrolytic polishing process, and a method for fabricating the ink-jet print head. The ink-jet print head is fabricated using an electrolytic polishing process, thereby achieving an accurate and inexpensive fabrication.

Abstract: There are disclosed methods for the prevention of misfit dislocation in a silicon wafer and the silicon wafer structure manufactured thereby. A method according to an embodiment comprises the steps of: depositing a blanket silicon oxide or silicon nitride on silicon wafer in a chemical vapor deposition process; selectively etching the silicon oxide or silicon nitride, to form a silicon oxide or silicon nitride pattern which is of close shape; and injecting the silicon wafer with impurities at a high density with the CVD silicon oxide or silicon nitride pattern serving as a mask, so as to form an impurity-blocked region is formed under the CVD silicon oxide or silicon nitride through the action of the mask. The misfit dislocation is propagated mainly from the edge of wafer and an impurity-blocked region can prevent the propagation. The propagation energy is virtually based on the tensile stress attributable to the implantation of impurity.

Abstract: A silicon on-insulator device wafer having a very thin monocrystalline film with uniform thickness. It is fabricated by vias technique in which a monocrystalline silicon film on an insulator is etched with a base silicon etching solution in an etch apparatus by applying a vias in such a way that the solution may serve as an anode and the substrate of SOI structure as a cathode. The presence of the insulator generates vacancies in a lower region of the monocrystalline silicon film and electrons in the substrate, so that the lower region charged with the vacancies is not removed by the base silicon etching solution, thereby leaving a highly uniform, thin monocrystalline silicon film.

Abstract: There are disclosed methods for the prevention of misfit dislocation in a silicon wafer and the silicon wafer structure manufactured thereby. A method according to an embodiment comprises the steps of: depositing a blanket silicon oxide or silicon nitride on silicon wafer in a chemical vapor deposition process; selectively etching the silicon oxide or silicon nitride, to form a silicon oxide or silicon nitride pattern which is of close shape; and injecting the silicon wafer with impurities at a high density with the CVD silicon oxide or silicon nitride pattern serving as a mask, so as to form an impurity-blocked region is formed under the CVD silicon oxide or silicon nitride through the action of the mask. The misfit dislocation is propagated mainly from the edge of wafer and an impurity-blocked region can prevent the propagation. The propagation energy is virtually based on the tensile stress attributable to the implantation of impurity.

Abstract: A heat generating type ink-jet print head including an ink supply passage for receiving an ink from an ink container, a micro chamber for storing the ink and nozzles, all being directly formed on a substrate, and a method for fabricating the ink-jet print head using an electrolytic polishing process, and a method for fabricating the ink-jet print head. The ink-jet print head is fabricated using an electrolytic polishing process, thereby achieving an accurate and inexpensive fabrication.

Abstract: A method for fabricating the polycrystal silicon TFT under a low temperature which has an improved electron mobility, comprises the steps of forming an oxide film on a substrate, depositing a polycrystal silicon on the oxide film and patterning the polycrystal silicon so that source and drain regions and a channel region remain, growing a gate insulating layer on the patterned polycrystal silicon by ECR plasma thermal oxidation, depositing a material for a gate on the whole surface and removing the material and the gate insulating layer in portions except for a gate region to form the gate, and performing ion implantation on the exposed areas of the polycrystal silicon to form the source and drain regions.

Abstract: A novel diffusion type transistor which is useful for relatively high-power and high-current applications and a method for manufacturing the transistor are disclosed.In constructing the transistor, the base under emitter has three zones, one of which is a buried layer such as used in the fabrication of bipolar integrated circuits. Two of the zones, including the buried layer base zone, are highly doped to provide a low resistivity base current path. The last zone is a low impurity concentration epitaxially grown base zone and which accepts and transports the injected minority carriers from the emitter to the collector. Hence, the emitter periphery is determined by the sum of the total PN junction boundary between the buried layer base zone, the epitaxially grown base zone and a diffused emitter.

Abstract: A charge-coupled device having a semiconductor substrate, a layer of insulation covering the substrate, and a plurality of spaced-apart electrodes formed from a doped, polycrystalline semiconductor material of a particular conductivity type includes regions of interelectrode material doped with an impurity of a conductivity type opposite to said particular conductivity type.