Patents by Inventor Choong Kit Wong
Choong Kit Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10224911Abstract: An integrated circuit (IC) device includes a first input/output (I/O) buffer circuit. The first input/output buffer circuit includes first and second groups of stacked transistors. The first group of stacked transistors transfer signals formatted in accordance with only one signal protocol from the group of signal protocols. The second group of stacked transistors transfers the signals formatted in accordance with more than one signal protocols. In addition, integrated circuit device also includes a second input/output buffer circuit. The second input/output buffer circuit includes third and fourth groups of stacked transistors. The third group of stacked transistors transfers the signals formatted in accordance to the first signal transmission protocol from the group of signal transmission protocols. The fourth group of stacked transistors transfers the signals formatted in accordance to the plurality of signal transmission protocols from the group of signal transmission protocols.Type: GrantFiled: March 31, 2016Date of Patent: March 5, 2019Assignee: Altera CorporationInventors: Tat Hin Tan, Choong Kit Wong, Ker Yon Lau, Hsiao Wei Su, Hoong Chin Ng
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Patent number: 10110225Abstract: An input/output (I/O) circuit for an integrated circuit includes an input-output terminal, a termination circuit and an impedance compensation circuit. The termination circuit includes a node that is coupled to the input-output terminal. The termination circuit exhibits substantially constant first impedance below a first frequency of signals received at the input-output terminal. Furthermore, the termination circuit exhibits second impedance that is less than the first impedance when signals having a second frequency that is higher than the first frequency are received at the input-output terminal. The impedance compensation circuit is coupled to the input-output terminal. The impedance compensation circuit compensates for differences between the first and second impendences when the signal having the second frequency that is higher than the first frequency is received at the input-output terminal.Type: GrantFiled: November 2, 2016Date of Patent: October 23, 2018Assignee: Altera CorporationInventors: Ker Yon Lau, Tat Hin Tan, Choong Kit Wong
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Patent number: 10103627Abstract: A packaged integrated circuit and method of forming the same. The package integrated circuit includes an integrated circuit formed on a semiconductor die affixed to a surface of a multi-layer substrate, and a switch-mode regulator formed on the semiconductor die (or another semiconductor die) affixed to the surface of the multi-layer substrate. The integrated circuit and the switch-mode regulator are integrated within a package to form the packaged integrated circuit.Type: GrantFiled: February 26, 2015Date of Patent: October 16, 2018Assignee: Altera CorporationInventors: Teik Wah Lim, Ashraf W. Lotfi, Choong Kit Wong, John Weld
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Patent number: 9793888Abstract: An output driver circuit includes a control circuit and first and second transistor legs that are coupled to an output pad. Each of the first and second transistor legs includes a pull-up transistor and a pull-down transistor. The control circuit is coupled to the first and second transistor legs. The control circuit enables the first transistor leg to generate an output signal at the output pad and disables the second transistor leg during a first phase of a cycle. The control circuit enables the second transistor leg to generate the output signal at the output pad and disables the first transistor leg during a second phase of the cycle. The control circuit repeats the first and the second phases of the cycle.Type: GrantFiled: March 14, 2016Date of Patent: October 17, 2017Assignee: Altera CorporationInventors: Tat Hin Tan, Yue-Song He, Choong Kit Wong
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Publication number: 20170264283Abstract: An output driver circuit includes a control circuit and first and second transistor legs that are coupled to an output pad. Each of the first and second transistor legs includes a pull-up transistor and a pull-down transistor. The control circuit is coupled to the first and second transistor legs. The control circuit enables the first transistor leg to generate an output signal at the output pad and disables the second transistor leg during a first phase of a cycle. The control circuit enables the second transistor leg to generate the output signal at the output pad and disables the first transistor leg during a second phase of the cycle. The control circuit repeats the first and the second phases of the cycle.Type: ApplicationFiled: March 14, 2016Publication date: September 14, 2017Applicant: Altera CorporationInventors: Tat Hin Tan, Yue-Song He, Choong Kit Wong
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Publication number: 20160254745Abstract: A packaged integrated circuit and method of forming the same. The package integrated circuit includes an integrated circuit formed on a semiconductor die affixed to a surface of a multi-layer substrate, and a switch-mode regulator formed on the semiconductor die (or another semiconductor die) affixed to the surface of the multi-layer substrate. The integrated circuit and the switch-mode regulator are integrated within a package to form the packaged integrated circuit.Type: ApplicationFiled: February 26, 2015Publication date: September 1, 2016Applicant: ALTERA CORPORATIONInventors: Teik Wah Lim, Ashraf W. Lotfi, Choong Kit Wong, John Weld
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Patent number: 8686758Abstract: I/O circuits and a method for transmitting different types of I/O signals are disclosed. An embodiment of the I/O circuit comprises multiple transistors with multiple switches coupled to the transistors. The switches may be used to selectively couple the transistors to a power source or to another transistor to form different transistor configurations. The transistors may be configured to form a parallel configuration or a stacked configuration. Stacking up transistors may reduce voltage swings in the transistors and subsequently reduce degradation in the transistors.Type: GrantFiled: April 14, 2009Date of Patent: April 1, 2014Assignee: Altera CorporationInventors: Ket Chiew Sia, Choong Kit Wong, Boon Jin Ang
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Patent number: 8151224Abstract: A method of designing at IC is described. In one embodiment, the method includes providing an option to select a mask layer set from a plurality of mask layer sets, the plurality of mask layer sets including a first mask layer set and a second mask layer set, where the second mask layer set is an alternative mask layer option to the first mask layer set. In one embodiment, the method further includes receiving a selection from a user choosing a mask layer set from the plurality of mask layer sets. In one embodiment, the receiving occurs after design of the IC and prior to fabrication of the IC. Also, in one embodiment, the plurality of mask layer sets are predetermined mask layer sets. In one embodiment, the first mask layer set is a standard threshold voltage (SVT) mask layer set and the second mask layer set is a high threshold voltage (HVT) mask layer set. In one embodiment, core devices of the SVT mask layer set are SVT devices and some periphery devices of the SVT mask layer set are HVT devices.Type: GrantFiled: December 29, 2008Date of Patent: April 3, 2012Assignee: Altera CorporationInventors: Boon Jin Ang, Kar Keng Chua, Choong Kit Wong, Kok Yoong Foo, Thow Pang Chong
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Patent number: 7787314Abstract: In mask programmable integrated circuit, such as a structured ASIC, a delay chain provides a delay that is set by a mask programmable switch. The delay chain receives an input to allow the delay mask programmed delay to be overridden using a JTAG controller. This allows testing of different delays. The input may also be provided by a fuse block, so that the fuse block can override the mask programmable switch, thus allowing a delay to be changes after mask programming.Type: GrantFiled: September 11, 2008Date of Patent: August 31, 2010Assignee: Altera CorporationInventors: Jun Pin Tan, Wei Yee Koay, Boon Jin Ang, Choong Kit Wong, Guang Sheng Soh
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Publication number: 20100061166Abstract: In mask programmable integrated circuit, such as a structured ASIC, a delay chain provides a delay that is set by a mask programmable switch. The delay chain receives an input to allow the delay mask programmed delay to be overridden using a JTAG controller. This allows testing of different delays. The input may also be provided by a fuse block, so that the fuse block can override the mask programmable switch, thus allowing a delay to be changes after mask programming.Type: ApplicationFiled: September 11, 2008Publication date: March 11, 2010Applicant: ALTERA CORPORATIONInventors: Jun Pin Tan, Wei Yee Koay, Boon Jin Ang, Choong Kit Wong, Guang Sheng Soh
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Patent number: 7265587Abstract: Methods and apparatus are provided for performing pre-emphasis of signals using buffer circuitry that is not dedicated to LVDS transmission. In an embodiment of the invention, pre-emphasis circuitry is provided to enable unused transistors of the buffer circuitry to increase the current that can be driven onto output signal lines, resulting in sharper signal transitions and improved signal integrity. In addition, circuitry can be provided that limits the duration of the pre-emphasis to a selected period of time, thereby conserving power and limiting the differential voltage between a given pair of transmitted signals.Type: GrantFiled: July 26, 2005Date of Patent: September 4, 2007Assignee: Altera CorporationInventors: Bee Yee Ng, Choong Kit Wong, Boon Jin Ang
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Patent number: 7180329Abstract: An adjustable level shifter with native and kicker transistors is provided. The level shifter provides high switching speeds, adjustable output voltage levels, and low jitter. The level shifter has first and second thick-oxide p-channel metal-oxide-semiconductor (PMOS) transistors, first and second thick-oxide native n-channel metal-oxide-semiconductor (NMOS) transistors, and first and second thin-oxide NMOS transistors. The first PMOS transistor, first native transistor, and first NMOS transistor are connected in series and the second PMOS transistor, second native transistor, and second NMOS transistor are connected in series. An input data signal and an inverted version of the input data signal drive the gates of the thin-oxide NMOS transistors. A node located between the first PMOS transistor and first native transistor is connected to an output data terminal. The kicker transistor is connected in parallel with the first PMOS transistor.Type: GrantFiled: April 20, 2005Date of Patent: February 20, 2007Assignee: Altera CorporationInventors: Ket Chiew Sia, Choong Kit Wong, Boon Haw Ooi, Kok Siong Tee
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Patent number: 6489817Abstract: A clock divider is described.Type: GrantFiled: September 26, 2001Date of Patent: December 3, 2002Assignee: Altera CorporationInventors: Choong Kit Wong, Sammy Cheung, Boon Jin Ang