Patents by Inventor Choong-Ryul Ryou
Choong-Ryul Ryou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160005624Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.Type: ApplicationFiled: August 4, 2015Publication date: January 7, 2016Inventors: Choong-Ryul Ryou, Hee-Sung Kang
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Patent number: 9111880Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.Type: GrantFiled: September 29, 2014Date of Patent: August 18, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Choong-Ryul Ryou, Hee-Sung Kang
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Publication number: 20150017804Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.Type: ApplicationFiled: September 29, 2014Publication date: January 15, 2015Inventors: Choong-Ryul Ryou, Hee-Sung Kang
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Patent number: 8846304Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.Type: GrantFiled: March 18, 2013Date of Patent: September 30, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Choong-Ryul Ryou, Hee-Sung Kang
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Publication number: 20130230979Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.Type: ApplicationFiled: March 18, 2013Publication date: September 5, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Choong-Ryul Ryou, Hee-Sung Kang
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Patent number: 8409787Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.Type: GrantFiled: March 7, 2011Date of Patent: April 2, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Choong-Ryul Ryou, Hee-Sung Kang
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Publication number: 20110159443Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.Type: ApplicationFiled: March 7, 2011Publication date: June 30, 2011Inventors: Choong-Ryul Ryou, Hee-Sung Kang
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Patent number: 7914973Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.Type: GrantFiled: June 25, 2008Date of Patent: March 29, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Choong-Ryul Ryou, Hee-Sung Kang
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Publication number: 20080261156Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.Type: ApplicationFiled: June 25, 2008Publication date: October 23, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Choong-Ryul Ryou, Hee-Sung Kang
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Publication number: 20080032483Abstract: In a trench isolation method, a semiconductor substrate having an N-MOS region and a P-MOS region is prepared. A first mask pattern exposing an N-MOS field region is formed on the N-MOS region, and a second mask pattern exposing a P-MOS field region is formed on the P-MOS region. A first photoresist pattern is formed to cover the P-MOS region and expose the N-MOS region. First impurity ions are implanted into the N-MOS region, using the first mask pattern and the first photoresist pattern as ion implantation masks, thereby forming a first impurity layer in the N-MOS field region. In this case, a portion of the first impurity layer is formed to extend below the first mask pattern. The first photoresist pattern is removed. The semiconductor substrate is etched using the first and second mask patterns as etch masks, thereby forming trenches in the N-MOS field region and the P-MOS field region and concurrently, forming a first impurity pattern of the first impurity layer remaining below the first mask pattern.Type: ApplicationFiled: October 5, 2007Publication date: February 7, 2008Applicant: Samsung Electronics Co., Ltd.Inventors: Hyuk-Ju Ryu, Heon-Jong Shin, Hee-Sung Kang, Choong-Ryul Ryou, Mu-Kyeng Jung, Kyung-Soo Kim
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Patent number: 7179714Abstract: There is provided a method of fabricating a MOS transistor having a fully silicided gate, including forming a gate pattern and gate spacers on a semiconductor substrate, the gate pattern including a lower gate pattern, an insulating layer pattern, and an upper gate pattern, which are sequentially stacked. Source/drain regions are formed by implanting impurity ions into an active region using the gate pattern and the gate spacers as ion implantation masks. Then, a protecting layer is formed on the semiconductor substrate having the gate pattern, and the protecting layer is planarized until the upper gate pattern is exposed. Then, by removing the exposed upper gate pattern and the insulating layer pattern, the lower gate pattern is exposed. Then, the protecting layer is selectively removed, thereby exposing the source/drain regions. The exposed lower gate pattern is fully converted to a gate silicide layer, and a silicide layer is concurrently formed on the surfaces of the source/drain regions.Type: GrantFiled: February 24, 2005Date of Patent: February 20, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: You-Jean Chang, Myoung-Hwan Oh, Hee-Sung Kang, Choong-Ryul Ryou
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Publication number: 20060240636Abstract: In a trench isolation method, a semiconductor substrate having an N-MOS region and a P-MOS region is prepared. A first mask pattern exposing an N-MOS field region is formed on the N-MOS region, and a second mask pattern exposing a P-MOS field region is formed on the P-MOS region. A first photoresist pattern is formed to cover the P-MOS region and expose the N-MOS region. First impurity ions are implanted into the N-MOS region, using the first mask pattern and the first photoresist pattern as ion implantation masks, thereby forming a first impurity layer in the N-MOS field region. In this case, a portion of the first impurity layer is formed to extend below the first mask pattern. The first photoresist pattern is removed. The semiconductor substrate is etched using the first and second mask patterns as etch masks, thereby forming trenches in the N-MOS field region and the P-MOS field region and concurrently, forming a first impurity pattern of the first impurity layer remaining below the first mask pattern.Type: ApplicationFiled: February 21, 2006Publication date: October 26, 2006Inventors: Hyuk-Ju Ryu, Heon-Jong Shin, Hee-Sung Kang, Choong-Ryul Ryou, Mu-Kyeng Jung, Kyung-Soo Kim
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Publication number: 20060194436Abstract: In a semiconductor device including a resistor and a method of fabricating the same, the semiconductor device includes an isolation insulating layer disposed in a semiconductor substrate to define at least two active regions spaced from each other. A well resistor pattern is disposed below the isolation insulating layer to connect the active regions. An upper resistor pattern is disposed on the isolation insulating layer between the active regions. A resistor connector electrically connects a selected one of the active regions with the upper resistor pattern so that the well resistor pattern and the upper resistor pattern are connected in series.Type: ApplicationFiled: February 14, 2006Publication date: August 31, 2006Inventors: Myoung-Hwan Oh, Hee-Sung Kang, Choong-Ryul Ryou
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Patent number: 7045429Abstract: In a method of manufacturing a semiconductor device, a device including gate electrodes and asymmetric source and drain regions is formed by employing a semiconductor layer structure. The short channel effect is prevented in the resulting device even though the gate electrodes are of a dimension on the order of nanometers. Additionally, the gate electrodes and asymmetric source and drain regions of the semiconductor device may be precisely formed to have dimensions on the nanometer scale because a semiconductor layer structure is used in the process for manufacturing the semiconductor device.Type: GrantFiled: February 2, 2005Date of Patent: May 16, 2006Assignee: Samsung Electronics, Co., Ltd.Inventors: Jin-Hua Liu, Hee-Sung Kang, Choong-Ryul Ryou
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Publication number: 20050191833Abstract: There is provided a method of fabricating a MOS transistor having a fully silicided gate, including forming a gate pattern and gate spacers on a semiconductor substrate, the gate pattern including a lower gate pattern, an insulating layer pattern, and an upper gate pattern, which are sequentially stacked. Source/drain regions are formed by implanting impurity ions into an active region using the gate pattern and the gate spacers as ion implantation masks. Then, a protecting layer is formed on the semiconductor substrate having the gate pattern, and the protecting layer is planarized until the upper gate pattern is exposed. Then, by removing the exposed upper gate pattern and the insulating layer pattern, the lower gate pattern is exposed. Then, the protecting layer is selectively removed, thereby exposing the source/drain regions. The exposed lower gate pattern is fully converted to a gate silicide layer, and a silicide layer is concurrently formed on the surfaces of the source/drain regions.Type: ApplicationFiled: February 24, 2005Publication date: September 1, 2005Inventors: You-Jean Chang, Myoung-Hwan Oh, Hee-Sung Kang, Choong-Ryul Ryou
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Publication number: 20050176207Abstract: In a method of manufacturing a semiconductor device, a device including gate electrodes and asymmetric source and drain regions is formed by employing a semiconductor layer structure. The short channel effect is prevented in the resulting device even though the gate electrodes are of a dimension on the order of nanometers. Additionally, the gate electrodes and asymmetric source and drain regions of the semiconductor device may be precisely formed to have dimensions on the nanometer scale because a semiconductor layer structure is used in the process for manufacturing the semiconductor device.Type: ApplicationFiled: February 2, 2005Publication date: August 11, 2005Inventors: Jin-Hua Liu, Hee-Sung Kang, Choong-Ryul Ryou
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Publication number: 20050142497Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.Type: ApplicationFiled: December 22, 2004Publication date: June 30, 2005Inventors: Choong-Ryul Ryou, Hee-Sung Kang