Patents by Inventor Choong-seob SHIN

Choong-seob SHIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD OF FORMING SEMICONDUCTOR DEVICE USING POLISHING RESISTANCE PATTERN
    Publication number: 20190341358
    Abstract: A method of forming a semiconductor device, includes: forming a design pattern on a substrate, wherein the design pattern protrudes from the substrate; forming a filling layer on the substrate, wherein the filling layer at least partially covers the design pattern; forming a polishing resistance pattern adjacent to the design pattern in the filling layer using a laser irradiation process and/or an ion implantation process; and removing the filling layer using a chemical mechanical polishing (CMP) process to expose the design pattern.
    Type: Application
    Filed: January 21, 2019
    Publication date: November 7, 2019
    Inventors: YANG HEE LEE, Jong Hyuk Park, Jin Woo Bae, Choong Seob Shin, Hyo Jin Oh, Bo Un Yoon, Il Young Yoon, Hee Sook Cheon
  • Methods of manufacturing semiconductor devices using alignment marks to align layers
    Patent number: 9831186
    Abstract: A method of manufacturing a semiconductor device includes forming a first alignment mark trench in a first material layer on a substrate. A first alignment mark via may then be formed by etching a second material layer that is underneath the first material layer, where the first alignment mark via is positioned to communicate with the first alignment mark trench. Then, a trench-via-merged-type first alignment mark may be formed by filling the first alignment mark trench and the first alignment mark via with a light reflection material layer.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: November 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-hyun Park, Byoung-ho Kwon, Dong-chan Kim, Choong-seob Shin, Jong-su Kim, Bo-un Yoon
  • METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING ALIGNMENT MARKS TO ALIGN LAYERS
    Publication number: 20160027739
    Abstract: A method of manufacturing a semiconductor device includes forming a first alignment mark trench in a first material layer on a substrate. A first alignment mark via may then be formed by etching a second material layer that is underneath the first material layer, where the first alignment mark via is positioned to communicate with the first alignment mark trench. Then, a trench-via-merged-type first alignment mark may be formed by filling the first alignment mark trench and the first alignment mark via with a light reflection material layer.
    Type: Application
    Filed: June 11, 2015
    Publication date: January 28, 2016
    Inventors: Ki-hyun Park, Byoung-ho KWON, Dong-chan KIM, Choong-seob SHIN, Jong-su KIM, Bo-un YOON