Abstract: A TFT that provides an efficient layout, a fabrication method thereof, an LCD device having the TFT, and a fabrication method thereof are provided. The TFT has a gate electrode and source/drain electrodes with an active layer interposed. The source electrodes and the drain electrodes are alternated in a vertical direction and a horizontal direction. Thus, the same source electrodes and the same drain electrodes are arranged in a diagonal direction. Source lines are connected with the source electrodes arranged in a diagonal direction and drain lines are connected with the drain electrodes arranged in a diagonal direction. Since a channel width is formed between the source electrode and adjacent drain electrodes, the channel width can be maximized within a limited area. Also, the source lines and the drain lines are arranged in a diagonal direction, so that an area use rate is maximized.

Abstract: A liquid crystal display device includes a liquid crystal display panel. A drive circuit part is formed in the display panel. The drive circuit has a switching device with thin film transistors. The transistors commonly use one gate electrode and are connected in parallel. The switching device includes a gate electrode, a gate insulating film covering the gate electrode, a semiconductor pattern which overlaps the gate electrode with the gate insulating film therebetween, and source and drain electrodes which are formed on the semiconductor pattern and face each other. The source and drain electrodes, as well as a channel between the source and drain electrodes, are bent in the same direction.

Abstract: Provided is a method of crystallizing/activating a polysilicon layer and a method of fabricating a thin film transistor having the same polysilicon layer, in which when a gate material is patterned to form a gate electrode and define source/drain regions, the gate material on source/drain regions partially remains, so that crystallizing and activating processes are performed at the same time.

Abstract: Provided is a method for planarizing a polysilicon surface grown by means of a sequential lateral solidification method, which comprises the steps of: crystallizing an amorphous silicon having a predetermined thickness formed on a substrate into the polysilicon layer by means of the sequential lateral solidification method; and planarizing the polysilicon layer by means of a laser having an energy density for converting partially melted polysilicon into fully melted polysilicon, so that electrical characteristics of element may be improved when the polysilicon thin film transistor is fabricated using the planarization process.