Abstract: The invention relates to a method and apparatus for controlling a high voltage generator during wafer burn-in. The method includes generating an enable signal for enabling a high voltage generator responsive to a mode signal, e.g., a wafer burn-in test mode. The method provides an external voltage to a semiconductor memory device through a pad responsive to the enable signal. The method varies a high voltage level being output from the high voltage generator in response to a reference voltage level.

Abstract: The invention relates to a method and apparatus for controlling a high voltage generator during wafer burn-in. The method includes generating an enable signal for enabling a high voltage generator responsive to a mode signal, e.g., a wafer burn-in test mode. The method provides an external voltage to a semiconductor memory device through a pad responsive to the enable signal. The method varies a high voltage level being output from the high voltage generator in response to a reference voltage level.

Abstract: The invention relates to a method and apparatus for controlling a high voltage generator during wafer burn-in. The method includes generating an enable signal for enabling a high voltage generator responsive to a mode signal, e.g., a wafer bum-in test mode. The method provides an external voltage to a semiconductor memory device through a pad responsive to the enable signal. The method varies a high voltage level being output from the high voltage generator in response to a reference voltage level.

Abstract: The invention relates to a method and apparatus for controlling a high voltage generator during wafer burn-in. The method includes generating an enable signal for enabling a high voltage generator responsive to a mode signal, e.g., a wafer bum-in test mode. The method provides an external voltage to a semiconductor memory device through a pad responsive to the enable signal. The method varies a high voltage level being output from the high voltage generator in response to a reference voltage level.

Abstract: In a sense amplifier control circuit and method for a semiconductor memory device, a row address strobe (RAS) signal delay unit delays a RAS signal for a predetermined period of time. A sense amplifier control signal generator generates first and second sense amplifier control signals, responsive to the delayed RAS signal and a test mode control signal, which are enabled at the same time or at different periods depending on operation modes of the memory device. First and second sense amplifiers respectively sense and amplify the potential of odd-numbered and even-numbered bit line pairs of the memory device, responsive to the first and second sense amplifier control signals. The probability and accuracy of detecting bit line bridge defects are increased, because the times for sensing two adjacent bit lines are different.

Abstract: In a sense amplifier control circuit and method for a semiconductor memory device, a row address strobe (RAS) signal delay unit delays a RAS signal for a predetermined period of time. A sense amplifier control signal generator generates first and second sense amplifier control signals, responsive to the delayed RAS signal and a test mode control signal, which are enabled at the same time or at different periods depending on operation modes of the memory device. First and second sense amplifiers respectively sense and amplify the potential of odd-numbered and even-numbered bit line pairs of the memory device, responsive to the first and second sense amplifier control signals. The probability and accuracy of detecting bit line bridge defects are increased, because the times for sensing two adjacent bit lines are different.

Abstract: Integrated circuit memory devices include an array of memory cells and a row address generator circuit which generates first and second different sequences of addresses during first and second refresh modes, respectively, and also repeats at least one of the addresses in the first sequence as an address in the second sequence when transitioning from the first refresh mode to the second refresh mode. The generator circuit may also perform the function of generating row addresses during the first and second refresh modes with the most significant bit of a row address being toggled with each consecutive row address during the first refresh mode. The first refresh mode may be a CAS-before-RAS refresh mode, the second refresh mode may be a self-refresh mode and the address in at least one of the first and second periods of the self-refresh mode may be equivalent to an address in the last period of a preceding CAS-before-RAS refresh mode when transitioning from the first refresh mode to the second refresh mode.