Patents by Inventor Choong-Young Oh

Choong-Young Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8912097
    Abstract: A method of patterning a substrate comprises providing an array of resist features defined by a first pitch and a first gap width between adjacent resist features. Particles are introduced into the array of resist features, wherein the array of resist features becomes hardened. The introduction of particles may cause a reduction in critical dimension of the resist features. Sidewalls are provided on side portions of hardened resist features. Subsequent to the formation of the sidewalls, the hardened resist features are removed, leaving an array of isolated sidewalls disposed on the substrate. The sidewall array provides a mask for double patterning of features in the substrate layers disposed below the sidewalls, wherein an array of features formed in the substrate has a second pitch equal to half that of the first pitch.
    Type: Grant
    Filed: August 19, 2010
    Date of Patent: December 16, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Patrick M. Martin, Steven Carlson, Choong-Young Oh, Jung-Wook Park
  • Publication number: 20110300711
    Abstract: A method of patterning a substrate comprises providing an array of resist features defined by a first pitch and a first gap width between adjacent resist features. Particles are introduced into the array of resist features, wherein the array of resist features becomes hardened. The introduction of particles may cause a reduction in critical dimension of the resist features. Sidewalls are provided on side portions of hardened resist features. Subsequent to the formation of the sidewalls, the hardened resist features are removed, leaving an array of isolated sidewalls disposed on the substrate. The sidewall array provides a mask for double patterning of features in the substrate layers disposed below the sidewalls, wherein an array of features formed in the substrate has a second pitch equal to half that of the first pitch.
    Type: Application
    Filed: August 19, 2010
    Publication date: December 8, 2011
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Patrick M. Martin, Steven Carlson, Choong-Young Oh, Jung-Wook Park