Abstract: A semiconductor device includes a substrate, upper impurity regions in upper portions of the substrate, metal electrodes electrically connected to the upper impurity regions, metal silicide layers between the metal electrodes and the upper impurity regions, and a lower impurity region in a lower portion of the substrate. A method of fabricating the semiconductor device and an apparatus used in fabricating the semiconductor device is also provided.

Abstract: A semiconductor device includes a substrate, upper impurity regions in upper portions of the substrate, metal electrodes electrically connected to the upper impurity regions, metal silicide layers between the metal electrodes and the upper impurity regions, and a lower impurity region in a lower portion of the substrate. A method of fabricating the semiconductor device and an apparatus used in fabricating the semiconductor device is also provided.

Abstract: A semiconductor device includes a substrate, upper impurity regions in upper portions of the substrate, metal electrodes electrically connected to the upper impurity regions, metal silicide layers between the metal electrodes and the upper impurity regions, and a lower impurity region in a lower portion of the substrate. A method of fabricating the semiconductor device and an apparatus used in fabricating the semiconductor device is also provided.

Abstract: A semiconductor device includes a substrate, upper impurity regions in upper portions of the substrate, metal electrodes electrically connected to the upper impurity regions, metal silicide layers between the metal electrodes and the upper impurity regions, and a lower impurity region in a lower portion of the substrate. A method of fabricating the semiconductor device and an apparatus used in fabricating the semiconductor device is also provided.

Abstract: A method of forming a metal silicide layer can include implanting dopants to a first depth below a surface of a semiconductor substrate including an active area. A metal-silicon composite layer can be formed on the semiconductor substrate and the metal-silicon composite layer can be silicided to form the metal silicide layer on the active area.

Abstract: The present invention relates to a high load and high precision polygonal guide, and to a picker actuator using same, wherein the polygonal guide includes: an integrated ball cage designed and formed in a polygon and having a plurality of ball receiving holes formed on each side of the polygonal ball cage for receiving balls; a housing having a polygonal through hole for rolling motion such that, after the balls are inserted into the ball receiving holes formed on each side of the polygonal ball cage, the balls cannot escape from the ball receiving holes; and a guide post inserted and fitted inside the polygonal ball cage into which the balls are inserted and fitted, whereby the guide post or the housing reciprocates in a straight line by the rolling motion of the balls.

Abstract: A method of forming a metal silicide layer can include implanting dopants to a first depth below a surface of a semiconductor substrate including an active area. A metal-silicon composite layer can be formed on the semiconductor substrate and the metal-silicon composite layer can be silicided to form the metal silicide layer on the active area.

Abstract: A semiconductor device includes a substrate, upper impurity regions in upper portions of the substrate, metal electrodes electrically connected to the upper impurity regions, metal silicide layers between the metal electrodes and the upper impurity regions, and a lower impurity region in a lower portion of the substrate. A method of fabricating the semiconductor device and an apparatus used in fabricating the semiconductor device is also provided.

Abstract: An optical switching device includes a substrate having an optical waveguide thereon, and a phase transition pattern in or on a portion of the optical waveguide. The phase transition pattern includes a material that is configured to be switched between insulating and conductive states responsive to a stimulus. At least one conductive element on the substrate directly contacts the phase transition pattern to provide the stimulus to the phase transition pattern. Related fabrication methods are also discussed.

Abstract: A semiconductor device includes a first gate structure on a first region of a substrate and a second gate structure on a second region of the substrate, a first impurity region on an upper portion of the substrate adjacent to the first gate structure and a second impurity region on an upper portion of the substrate adjacent to the second gate structure, a first metal silicide layer on the first impurity region, a Fermi level pinning layer on the second impurity region, a second metal silicide layer on the Fermi level pinning layer, and a first contact plug on the first metal silicide layer and a second contact plug on the second metal silicide layer. The Fermi level pinning layer pins a Fermi level of the second metal silicide layer to a given energy level.

Abstract: The present invention relates to a high load and high precision polygonal guide, and to a picker actuator using same, wherein the polygonal guide includes: an integrated ball cage designed and formed in a polygon and having a plurality of ball receiving holes formed on each side of the polygonal ball cage for receiving balls; a housing having a polygonal through hole for rolling motion such that, after the balls are inserted into the ball receiving holes formed on each side of the polygonal ball cage, the balls cannot escape from the ball receiving holes; and a guide post inserted and fitted inside the polygonal ball cage into which the balls are inserted and fitted, whereby the guide post or the housing reciprocates in a straight line by the rolling motion of the balls.

Abstract: A non-volatile memory device including a variable resistance material is provided. The non-volatile memory device may include a buffer layer, a variable resistance material layer and/or an upper electrode, for example, sequentially formed on a lower electrode. A schottky barrier may be formed on an interface between the buffer layer and the lower electrode. The variable resistance material layer may be formed with a variable resistance property.

Abstract: Integrated circuit devices include thermal image sensors that utilize quantum dots therein to provide negative resistance characteristics to at least portions of the sensors. The thermal image sensor may include a sensing unit configured to absorb radiation incident on a first surface thereof and first and second electrodes electrically coupled to the sensing unit. The sensing unit includes a plurality of quantum dots therein, which may extend between the first and second electrodes. These quantum dots may be configured to impart a negative resistance characteristic to the sensing unit. In particular, the sensing unit may include a sensing layer having first and second opposing ends, which are electrically coupled to the first and second electrodes, respectively, and the plurality of quantum dots may be distributed within the sensing layer.

Abstract: A non-volatile memory device includes: at least one horizontal electrode; at least one vertical electrode disposed to intersect the at least one horizontal electrode at an intersection region; at least one data layer disposed at the intersection region and having a conduction-insulation transition property; and at least one anti-fuse layer connected in series with the at least one data layer.

Abstract: A non-volatile variable resistance memory device and a method of fabricating the same are provided. The non-volatile variable resistance memory device may include a lower electrode, a buffer layer on the lower electrode, an oxide layer on the buffer layer and an upper electrode on the oxide layer. The buffer layer may be composed of an oxide and the oxide layer may have variable resistance characteristics.

Abstract: A nonvolatile memory device may include a lower electrode, an oxide layer including an amorphous alloy metal oxide disposed on the lower electrode, and a diode structure disposed on the oxide layer.

Abstract: A non-volatile memory device includes a first oxide layer, a second oxide layer and a buffer layer formed on a lower electrode. An upper electrode is formed on the buffer layer. In one example, the lower electrode is composed of at least one of Pt, Ru, Ir, IrOx and an alloy thereof, the second oxide layer is a transition metal oxide, the buffer layer is composed of a p-type oxide and the upper electrode is composed of a material selected from Ni, Co, Cr, W, Cu or an alloy thereof.

Abstract: A nonvolatile memory device includes at least one switching device and at least one storage node electrically connected to the at least one switching device. The at least one storage node includes a lower electrode, one or more oxygen-deficient metal oxide layers, one or more data storage layers, and an upper electrode. At least one of the one or more metal oxide layers is electrically connected to the lower electrode. At least one of the one or more data storage layers is electrically connected to at least one of the one or more metal oxide layers. The upper electrode is electrically connected to at least one of the one or more data storage layers. A method of manufacturing the nonvolatile memory device includes preparing the at least one switching device and forming the lower electrode, one or more metal oxide layers, one or more data storage layers, and upper electrode.

Abstract: Integrated circuit devices include thermal image sensors that utilize quantum dots therein to provide negative resistance characteristics to at least portions of the sensors. The thermal image sensor may include a sensing unit configured to absorb radiation incident on a first surface thereof and first and second electrodes electrically coupled to the sensing unit. The sensing unit includes a plurality of quantum dots therein, which may extend between the first and second electrodes. These quantum dots may be configured to impart a negative resistance characteristic to the sensing unit. In particular, the sensing unit may include a sensing layer having first and second opposing ends, which are electrically coupled to the first and second electrodes, respectively, and the plurality of quantum dots may be distributed within the sensing layer.

Abstract: A non-volatile memory device includes: at least one horizontal electrode; at least one vertical electrode disposed to intersect the at least one horizontal electrode at an intersection region; at least one data layer disposed at the intersection region and having a conduction-insulation transition property; and at least one anti-fuse layer connected in series with the at least one data layer.