Abstract: Techniques are provided for classifying and correcting errors in a bit sequence. At a memory control device, access is requested to a first bit sequences that is stored in a bit sequence database of a memory component and associated with an address. An error is detected in the first bit sequence, and the address associated with the bit sequence is compared to addresses stored in an address database of a content addressable memory component to determine if there is a match. When there is a match, the error is classified as a hard bit error. When there is not a match, the error is classified as a soft bit error.

Abstract: Techniques are provided for classifying and correcting errors in a bit sequence. At a memory control device, access is requested to a first bit sequences that is stored in a bit sequence database of a memory component and associated with an address. An error is detected in the first bit sequence, and the address associated with the bit sequence is compared to addresses stored in an address database of a content addressable memory component to determine if there is a match. When there is a match, the error is classified as a hard bit error. When there is not a match, the error is classified as a soft bit error.

Abstract: In one embodiment, an apparatus includes a first memory layer oriented in a first planar orientation, a second memory layer oriented in a second planar orientation, a third memory layer oriented in the first planar orientation; and a connector that is connected to the first memory layer at an electrical contact of the first memory layer and to the third memory layer at an electrical contact of the third memory layer, where the connector is unconnected to the second memory layer. At least one of the electrical contact of the first memory layer and the electrical contact of the third memory layer comprises a through-layer via. The second planar orientation is angularly offset a predetermined number of degrees from the first planar orientation.

Abstract: In one embodiment, an apparatus includes a first memory layer oriented in a first planar orientation, a second memory layer oriented in a second planar orientation, a third memory layer oriented in the first planar orientation; and a connector that is connected to the first memory layer at an electrical contact of the first memory layer and to the third memory layer at an electrical contact of the third memory layer, where the connector is unconnected to the second memory layer. At least one of the electrical contact of the first memory layer and the electrical contact of the third memory layer comprises a through-layer via. The second planar orientation is angularly offset a predetermined number of degrees from the first planar orientation.

Abstract: A memory architecture and a method of operating the same can provide a substantially constant data valid window (DVW) irrespective of a temperature for the memory device. Generally, a memory device can receive an access request, determine a temperature of the memory device, and switch a number of delay elements in an output buffer in response to the temperature of the memory device. In one embodiment, a memory device can have a multi-stage input-output (I/O) buffer and an automatic temperature compensated circuit that samples a temperature of the memory and then switches a number of delay elements in the I/O buffer into a data path between the memory and the output to provide a substantially constant DVW over changes in temperature.