Patents by Inventor Chor-Yin Chia
Chor-Yin Chia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8384650Abstract: A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each voltage storage device in a first group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. Similarly, each voltage storage device in a second group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the voltage storage devices in the first group and a second input connected to an output of a corresponding one of the voltage storage devices in the second group.Type: GrantFiled: February 2, 2011Date of Patent: February 26, 2013Assignee: Intersil Americas Inc.Inventor: Chor Yin Chia
-
Patent number: 8115755Abstract: Provided herein are methods and configurations for use with systems that drive or otherwise control displays (e.g., LCD displays). Such systems often include devices (e.g., buffers, DACs, ADCs, etc.) that require a sufficiently high bias current to enable the device to have a sufficiently fast slew rate and settling time, which may consume an undesirable high amount of power. Embodiments of the present invention adjust such bias current to reduce power consumption. A first bias current level is provided to the device when an input to, and a corresponding output from, the device are to transition from one level to another. A second bias current level is provided to the device when the input to, and the corresponding output from, the device are not to transition from one level to another, where the second bias current level is lower than the first bias current level.Type: GrantFiled: December 12, 2006Date of Patent: February 14, 2012Assignee: Intersil Americas Inc.Inventor: Chor-Yin Chia
-
Publication number: 20110273430Abstract: In an embodiment, a voltage level shifter circuit includes a first terminal configured to be connected to a high voltage supply rail (Vs+), a second terminal configured to be connected to a low voltage supply rail (Vs?), and an output voltage (VOUT) terminal. The voltage level shifter can also include a compensation voltage (VCOMP) node. Additionally, the voltage level shifter includes a plurality of switches configurable in a plurality of configurations, and control circuitry configured to control the switches so that in at least one of the configurations a load connected to the output voltage (VOUT) terminal does not draw any power from the low voltage supply rail (Vs?) and the high voltage supply rail (Vs+). The load can be, e.g., a gate drive circuit of a display panel, such as a thin film transistor-liquid crystal display (TFT-LCD) panel, but is not limited thereto.Type: ApplicationFiled: February 4, 2011Publication date: November 10, 2011Applicant: INTERSIL AMERICAS INC.Inventors: Chor Yin Chia, Hong Joong Kim
-
Publication number: 20110122056Abstract: A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each voltage storage device in a first group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. Similarly, each voltage storage device in a second group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the voltage storage devices in the first group and a second input connected to an output of a corresponding one of the voltage storage devices in the second group.Type: ApplicationFiled: February 2, 2011Publication date: May 26, 2011Applicant: INTERSIL AMERICAS INC.Inventor: Chor Yin Chia
-
Patent number: 7907109Abstract: A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each voltage storage device in a first group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. Similarly, each voltage storage device in a second group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the voltage storage devices in the first group and a second input connected to an output of a corresponding one of the voltage storage devices in the second group.Type: GrantFiled: September 29, 2006Date of Patent: March 15, 2011Assignee: Intersil Americas Inc.Inventor: Chor Yin Chia
-
Patent number: 7728807Abstract: Techniques are provided for producing two output voltages that are substantially symmetric about a middle voltage (VCOM), based on a digital data value stored in a register. A first output voltage is produced based on the digital data value stored in the register. Additionally, the digital data value stored in the register is converted (e.g., by determining its 2's compliment) to a second digital data value, which is used to produce a second output voltage that is substantially symmetric about VCOM with the first output voltage. Alternatively, the digital data value stored in the register is provided to two different DACs that have their pair of reference voltages swapped (where the reference voltages are symmetric about VCOM), which will result in the outputs of the DACs being substantially symmetric about VCOM.Type: GrantFiled: February 1, 2006Date of Patent: June 1, 2010Inventor: Chor Yin Chia
-
Patent number: 7385544Abstract: A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each sample-and-hold circuit in a first group of N sample-and-hold (S/H) circuits is connected to a corresponding output of the analog demultiplexer. Similarly, each S/H circuit in a second group of N S/H circuits is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the S/H circuits in the first group and a second input connected to an output of a corresponding one of the S/H circuits in the second group.Type: GrantFiled: March 1, 2007Date of Patent: June 10, 2008Assignee: Intersil Americas Inc.Inventor: Chor-Yin Chia
-
Publication number: 20080079706Abstract: Provided herein are methods and configurations for use with systems that drive or otherwise control displays (e.g., LCD displays). Such systems often include devices (e.g., buffers, DACs, ADCs, etc.) that require a sufficiently high bias current to enable the device to have a sufficiently fast slew rate and settling time, which may consume an undesirable high amount of power. Embodiments of the present invention adjust such bias current to reduce power consumption. A first bias current level is provided to the device when an input to, and a corresponding output from, the device are to transition from one level to another. A second bias current level is provided to the device when the input to, and the corresponding output from, the device are not to transition from one level to another, where the second bias current level is lower than the first bias current level.Type: ApplicationFiled: December 12, 2006Publication date: April 3, 2008Applicant: INTERSIL AMERICAS INC.Inventor: Chor-Yin Chia
-
Patent number: 7193551Abstract: A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each sample-and-hold circuit in a first group of N sample-and-hold (S/H) circuits is connected to a corresponding output of the analog demultiplexer. Similarly, each S/H circuit in a second group of N S/H circuits is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the S/H circuits in the first group and a second input connected to an output of a corresponding one of the S/H circuits in the second group.Type: GrantFiled: August 19, 2005Date of Patent: March 20, 2007Assignee: Intersil Americas Inc.Inventor: Chor Yin Chia
-
Publication number: 20070018936Abstract: A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each voltage storage device in a first group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. Similarly, each voltage storage device in a second group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the voltage storage devices in the first group and a second input connected to an output of a corresponding one of the voltage storage devices in the second group.Type: ApplicationFiled: September 29, 2006Publication date: January 25, 2007Applicant: Intersil Americas Inc.Inventor: Chor Yin Chia
-
Patent number: 7002498Abstract: The analog demultiplexer (FIG. 6) includes an input amplifier (A1), and output amplifiers (AMP1–AMPN). The output and inverting (?) input of amplifiers (AMP1–AMPN) are connected by a respective capacitor (C1–CN). Switches (S1a, S1b, etc.) connect the output of amplifier (A1) to the inverting input of one of (AMP1–AMPN). Switches (S2a, S2b, etc.) connect the output of one of (AMP1–AMPN) to the non-inverting input of the amplifier A1. Switches (S2a, S2b, etc.) and (S1a, S1b, etc.) open and close together in pairs. With feedback from the output of (AMP1–AMPN) through (A1), the gain and any offset of (AMP1–AMPN) is divided down by the gain of (A1). Amplifier (A1) has capacitors (CS1 and CS2) connected to its inputs. Switch (S50) connects the inverting input of amplifier (A1) to its output, and switch (S40) connects the non-inverting input of (A1) to a voltage reference (VREF) matching (VREF) applied to (AMP2). Switches (S30) and (S35) connect (CS1) and (CS2) to the demultiplexer input (2).Type: GrantFiled: April 11, 2005Date of Patent: February 21, 2006Assignee: Elantec Semiconductor, Inc.Inventor: Chor-Yin Chia
-
Publication number: 20050190090Abstract: The analog demultiplexer (FIG. 6) includes an input amplifier (A1), and output amplifiers (AMP1-AMPN). The output and inverting (?) input of amplifiers (AMP1-AMPN) are connected by a respective capacitor (C1-CN). Switches (S1a, S1b, etc.) connect the output of amplifier (A1) to the inverting input of one of (AMP1-AMPN). Switches (S2a, S2b, etc.) connect the output of one of (AMP1-AMPN) to the non-inverting input of the amplifier A1. Switches (S2a, S2b, etc.) and (S1a, S1b, etc.) open and close together in pairs. With feedback from the output of (AMP1-AMPN) through (A1), the gain and any offset of (AMP1-AMPN) is divided down by the gain of (A1). Amplifier (A1) has capacitors (CS1 and CS2) connected to its inputs. Switch (S50) connects the inverting input of amplifier (A1) to its output, and switch (S40) connects the non-inverting input of (A1) to a voltage reference (VREF) matching (VREF) applied to (AMP2). Switches (S30) and (S35) connect (CS1) and (CS2) to the demultiplexer input (2).Type: ApplicationFiled: April 11, 2005Publication date: September 1, 2005Applicant: Intersil Americas Inc.Inventor: Chor-Yin Chia
-
Patent number: 6897800Abstract: The analog demultiplexer (FIG. 6) includes an input amplifier (A1), and output amplifiers (AMP1-AMPN). The output and inverting (?) input of amplifiers (AMP1-AMPN) are connected by a respective capacitor (C1-CN). Switches (S1a, S1b, etc.) connect the output of amplifier (A1) to the inverting input of one of (AMP1-AMPN). Switches (S2a, S2b, etc.) connect the output of one of (AMP1-AMPN) to the non-inverting input of the amplifier A1. Switches (S2a, S2b, etc.) and (S1a, S1b, etc.) open and close together in pairs. With feedback from the output of (AMP1-AMPN) through (A1), the gain and any offset of (AMP1-AMPN) is divided down by the gain of (A1). Amplifier (A1) has capacitors (CS1 and CS2) connected to its inputs. Switch (S50) connects the inverting input of amplifier (A1) to its output, and switch (S40) connects the non-inverting input of (A1) to a voltage reference (VREF) matching (VREF) applied to (AMP2). Switches (S30) and (S35) connect (CS1) and (CS2) to the demultiplexer input (2).Type: GrantFiled: September 5, 2002Date of Patent: May 24, 2005Assignee: Elantec Semiconductor, Inc.Inventor: Chor-Yin Chia
-
Publication number: 20030043135Abstract: The analog demultiplexer (FIG. 6) includes an input amplifier (A1), and output amplifiers (AMP1-AMPN). The output and inverting (−) input of amplifiers (AMP1-AMPN) are connected by a respective capacitor (C1-CN). Switches (S1a, S1b, etc.) connect the output of amplifier (A1) to the inverting input of one of (AMP1-AMPN). Switches (S2a, S2b, etc.) connect the output of one of (AMP1-AMPN) to the non-inverting input of the amplifier A1. Switches (S2a, S2b, etc.) and (S1a, S1b, etc.) open and close together in pairs. With feedback from the output of (AMP1-AMPN) through (A1), the gain and any offset of (AMP1-AMPN) is divided down by the gain of (A1). Amplifier (A1) has capacitors (CS1 and CS2) connected to its inputs. Switch (S50) connects the inverting input of amplifier (A1) to its output, and switch (S40) connects the non-inverting input of (A1) to a voltage reference (VREF) matching (VREF) applied to (AMP2). Switches (S30) and (S35) connect (CS1) and (CS2) to the demultiplexer input (2).Type: ApplicationFiled: September 5, 2002Publication date: March 6, 2003Inventor: Chor-Yin Chia