Abstract: A system including first and second devices. The first device generates a trigger signal to test a memory. The memory has memory cells including first and second cells. The first and second cells are defective and are in a same row or column. The second device: tests the memory in response to the trigger signal and based on a first frequency; generates an error signal in response to detecting the first cell as defective; and based on the test, generates information including first and second addresses of the first and second cells. The first device, based on the error signal, receives the information at a second frequency. The second device compares the first and second addresses, and if a match, continues the test without reporting the second cell as defective. The first device, based on a number of times the first address is matched, repairs the row or the column.

Abstract: A system includes a first device, a first storage element, a comparator and a second device. The first device is configured to test memory cells in an array of memory cells to detect defective memory cells. The defective memory cells include a first memory cell and a second memory cell. The first storage element is configured to store a first address of the first memory cell. The comparator is configured to compare a second address of the second memory cell to the first address.

Abstract: The present invention provides a method and system for improving memory testing efficiency, raising the speed of memory testing, detecting memory failures occurring at the memory operating frequency, and reducing data reported for redundancy repair analysis. The memory testing system includes a first memory tester extracting failed memory location information from the memory at a higher memory operating frequency, an external memory tester receiving failed memory location information at a lower memory tester frequency, and an interface between the first memory tester and the external memory tester. The memory testing method uses data strobes at the memory tester frequency to clock out failed memory location information obtained at the higher memory operating frequency. In addition, the inventive method reports only enough information to the external memory tester for it to determine row, column and single bit failures repairable with the available redundant resources.

Abstract: The present invention provides a method and system for improving memory testing efficiency, raising the speed of memory testing, detecting memory failures occurring at the memory operating frequency, and reducing data reported for redundancy repair analysis. The memory testing system includes a first memory tester extracting failed memory location information from the memory at a higher memory operating frequency, an external memory tester receiving failed memory location information at a lower memory tester frequency, and an interface between the first memory tester and the external memory tester. The memory testing method uses data strobes at the memory tester frequency to clock out failed memory location information obtained at the higher memory operating frequency. In addition, the inventive method reports only enough information to the external memory tester for it to determine row, column and single bit failures repairable with the available redundant resources.

Abstract: The present invention provides a method and system for improving memory testing efficiency, raising the speed of memory testing, detecting memory failures occurring at the memory operating frequency, and reducing data reported for redundancy repair analysis. The memory testing system includes a first memory tester extracting failed memory location information from the memory at a higher memory operating frequency, an external memory tester receiving failed memory location information at a lower memory tester frequency, and an interface between the first memory tester and the external memory tester. The memory testing method uses data strobes at the memory tester frequency to clock out failed memory location information obtained at the higher memory operating frequency. In addition, the inventive method reports only enough information to the external memory tester for it to determine row, column and single bit failures repairable with the available redundant resources.