Patents by Inventor Chosaku Noda

Chosaku Noda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7319654
    Abstract: A signal can be detected based on a level slice system and detection delay time can be reduced by setting the recording density of a header field in a linear direction lower (coarse) than that of a user data recording field. Further, a signal can be detected based on the level slice system and detection delay time can be reduced by using a mark position form having a large detection margin as an information recording system of the header field. A readout error of a sector number due to a detection error is compensated for by recording address marks AM for attaining byte synchronization of the header field in both of a head portion and tail portion of information recorded in the header field.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: January 15, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Okamoto, Hideo Ando, Chosaku Noda, Yutaka Kashihara
  • Publication number: 20080008080
    Abstract: The length of a format modulation area in an address segment is limited to be 25% of the address-segment length or less, and the position of the format modulation area is selectable two possible positions. Subsequently, where a CLV optical-disk medium is used, wobble modulation areas in adjacent recording tracks do not overlap each other in the radius direction.
    Type: Application
    Filed: August 17, 2007
    Publication date: January 10, 2008
    Applicants: NEC CORPORATION, KABUSHIKI KAISHA TOSHIBA
    Inventors: Yutaka Yamanaka, Kinji Kayanuma, Chosaku Noda, Hiroharu Satoh, Hideaki Ohsawa
  • Patent number: 7317679
    Abstract: To improve the sync code detection reliability while simplifying the sync code position detection process, when a first pattern as a combination of three successive sync codes is compared with a second pattern in which the allocation of sync codes is shifted by one code from the first pattern, two or more sync codes are changed.
    Type: Grant
    Filed: November 27, 2006
    Date of Patent: January 8, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chosaku Noda, Hideo Ando
  • Patent number: 7313071
    Abstract: A signal can be detected based on a level slice system and detection delay time can be reduced by setting the recording density of a header field in a linear direction lower (coarse) than that of a user data recording field. Further, a signal can be detected based on the level slice system and detection delay time can be reduced by using a mark position form having a large detection margin as an information recording system of the header field. A readout error of a sector number due to a detection error is compensated for by recording address marks AM for attaining byte synchronization of the header field in both of a head portion and tail portion of information recorded in the header field.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: December 25, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Okamoto, Hideo Ando, Chosaku Noda, Yutaka Kashihara
  • Patent number: 7313082
    Abstract: To improve the sync code detection reliability while simplifying the sync code position detection process, when a first pattern as a combination of three successive sync codes is compared with a second pattern in which the allocation of sync codes is shifted by one code from the first pattern, two or more sync codes are changed.
    Type: Grant
    Filed: November 27, 2006
    Date of Patent: December 25, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chosaku Noda, Hideo Ando
  • Patent number: 7295507
    Abstract: A signal can be detected based on a level slice system and detection delay time can be reduced by setting the recording density of a header field in a linear direction lower (coarse) than that of a user data recording field. Further, a signal can be detected based on the level slice system and detection delay time can be reduced by using a mark position form having a large detection margin as an information recording system of the header field. A readout error of a sector number due to a detection error is compensated for by recording address marks AM for attaining byte synchronization of the header field in both of a head portion and tail portion of information recorded in the header field.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: November 13, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Okamoto, Hideo Ando, Chosaku Noda, Yutaka Kashihara
  • Patent number: 7292522
    Abstract: Address information is formed by M wobbles (integer M is the number of wobble waves) per bit as a basic unit, and is NRZ-recorded. Also, a sync signal used in sync detection of the address information is formed by N wobbles per bit as a basic unit (integer N is the number of wobble waves and M=2N). The sync signal with such configuration (6 wobbles per bit) is recorded on the head side of the address information (12 wobbles per bit). In this way, even when external noise is large, a modulated wobble signal can be demodulated more accurately.
    Type: Grant
    Filed: January 22, 2004
    Date of Patent: November 6, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuji Nagai, Chosaku Noda, Akihito Ogawa, Kazuto Kuroda
  • Patent number: 7289419
    Abstract: A signal can be detected based on a level slice system and detection delay time can be reduced by setting the recording density of a header field in a linear direction lower (coarse) than that of a user data recording field. Further, a signal can be detected based on the level slice system and detection delay time can be reduced by using a mark position form having a large detection margin as an information recording system of the header field. A readout error of a sector number due to a detection error is compensated for by recording address marks AM for attaining byte synchronization of the header field in both of a head portion and tail portion of information recorded in the header field.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: October 30, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Okamoto, Hideo Ando, Chosaku Noda, Yutaka Kashihara
  • Patent number: 7289420
    Abstract: A signal can be detected based on a level slice system and detection delay time can be reduced by setting the recording density of a header field in a linear direction lower (coarse) than that of a user data recording field. Further, a signal can be detected based on the level slice system and detection delay time can be reduced by using a mark position form having a large detection margin as an information recording system of the header field. A readout error of a sector number due to a detection error is compensated for by recording address marks AM for attaining byte synchronization of the header field in both of a head portion and tail portion of information recorded in the header field.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: October 30, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Okamoto, Hideo Ando, Chosaku Noda, Yutaka Kashihara
  • Patent number: 7289414
    Abstract: A signal can be detected based on a level slice system and detection delay time can be reduced by setting the recording density of a header field in a linear direction lower (coarse) than that of a user data recording field. Further, a signal can be detected based on the level slice system and detection delay time can be reduced by using a mark position form having a large detection margin as an information recording system of the header field. A readout error of a sector number due to a detection error is compensated for by recording address marks AM for attaining byte synchronization of the header field in both of a head portion and tail portion of information recorded in the header field.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: October 30, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Okamoto, Hideo Ando, Chosaku Noda, Yutaka Kashihara
  • Publication number: 20070247998
    Abstract: According to one embodiment, a disk shaped storage medium comprising a lead-in area at an inner periphery thereof, wherein the lead-in area has a recording management field which includes a write area which writes information specific to an apparatus having carried out recording into the storage medium.
    Type: Application
    Filed: June 22, 2007
    Publication date: October 25, 2007
    Inventors: Sumitaka MARUYAMA, Akihito Ogawa, Hideo Ando, Chosaku Noda
  • Patent number: 7286465
    Abstract: To improve the sync code detection reliability while simplifying the sync code position detection process, when a first pattern as a combination of three successive sync codes is compared with a second pattern in which the allocation of sync codes is shifted by one code from the first pattern, two or more sync codes are changed.
    Type: Grant
    Filed: November 27, 2006
    Date of Patent: October 23, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chosaku Noda, Hideo Ando
  • Patent number: 7272096
    Abstract: A signal can be detected based on a level slice system and detection delay time can be reduced by setting the recording density of a header field in a linear direction lower (coarse) than that of a user data recording field. Further, a signal can be detected based on the level slice system and detection delay time can be reduced by using a mark position form having a large detection margin as an information recording system of the header field. A readout error of a sector number due to a detection error is compensated for by recording address marks AM for attaining byte synchronization of the header field in both of a head portion and tail portion of information recorded in the header field.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: September 18, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Okamoto, Hideo Ando, Chosaku Noda, Yutaka Kashihara
  • Patent number: 7269121
    Abstract: A signal can be detected based on a level slice system and detection delay time can be reduced by setting the recording density of a header field in a linear direction lower (coarse) than that of a user data recording field. Further, a signal can be detected based on the level slice system and detection delay time can be reduced by using a mark position form having a large detection margin as an information recording system of the header field. A readout error of a sector number due to a detection error is compensated for by recording address marks AM for attaining byte synchronization of the header field in both of a head portion and tail portion of information recorded in the header field.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: September 11, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Okamoto, Hideo Ando, Chosaku Noda, Yutaka Kashihara
  • Patent number: 7269122
    Abstract: To improve the sync code detection reliability while simplifying the sync code position detection process, when a first pattern as a combination of three successive sync codes is compared with a second pattern in which the allocation of sync codes is shifted by one code from the first pattern, two or more sync codes are changed.
    Type: Grant
    Filed: November 27, 2006
    Date of Patent: September 11, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chosaku Noda, Hideo Ando
  • Publication number: 20070183300
    Abstract: Address information is formed by M wobbles (integer M is the number of wobble waves) per bit as a basic unit, and is NRZ-recorded. Also, a sync signal used in sync detection of the address information is formed by N wobbles per bit as a basic unit (integer N is the number of wobble waves and M=2N). The sync signal with such configuration (6 wobbles per bit) is recorded on the head side of the address information (12 wobbles per bit). In this way, even when external noise is large, a modulated wobble signal can be demodulated more accurately.
    Type: Application
    Filed: March 22, 2007
    Publication date: August 9, 2007
    Inventors: Yuji Nagai, Chosaku Noda, Akihito Ogawa, Kazuto Kuroda
  • Publication number: 20070159955
    Abstract: Address information is formed by M wobbles (integer M is the number of wobble waves) per bit as a basic unit, and is NRZ-recorded. Also, a sync signal used in sync detection of the address information is formed by N wobbles per bit as a basic unit (integer N is the number of wobble waves and M=2N). The sync signal with such configuration (6 wobbles per bit) is recorded on the head side of the address information (12 wobbles per bit). In this way, even when external noise is large, a modulated wobble signal can be demodulated more accurately.
    Type: Application
    Filed: March 22, 2007
    Publication date: July 12, 2007
    Inventors: Yuji Nagai, Chosaku Noda, Akihito Ogawa, Kazuto Kuroda
  • Publication number: 20070159956
    Abstract: Address information is formed by M wobbles (integer M is the number of wobble waves) per bit as a basic unit, and is NRZ-recorded. Also, a sync signal used in sync detection of the address information is formed by N wobbles per bit as a basic unit (integer N is the number of wobble waves and M=2N). The sync signal with such configuration (6 wobbles per bit) is recorded on the head side of the address information (12 wobbles per bit). In this way, even when external noise is large, a modulated wobble signal can be demodulated more accurately.
    Type: Application
    Filed: March 22, 2007
    Publication date: July 12, 2007
    Inventors: Yuji Nagai, Chosaku Noda, Akihito Ogawa, Kazuto Kuroda
  • Patent number: 7239591
    Abstract: A signal can be detected based on a level slice system and detection delay time can be reduced by setting the recording density of a header field in a linear direction lower (coarse) than that of a user data recording field. Further, a signal can be detected based on the level slice system and detection delay time can be reduced by using a mark position form having a large detection margin as an information recording system of the header field. A readout error of a sector number due to a detection error is compensated for by recording address marks AM for attaining byte synchronization of the header field in both of a head portion and tail portion of information recorded in the header field.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: July 3, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Okamoto, Hideo Ando, Chosaku Noda, Yutaka Kashihara
  • Publication number: 20070147211
    Abstract: To improve the sync code detection reliability while simplifying the sync code position detection process, when a first pattern as a combination of three successive sync codes is compared with a second pattern in which the allocation of sync codes is shifted by one code from the first pattern, two or more sync codes are changed.
    Type: Application
    Filed: November 27, 2006
    Publication date: June 28, 2007
    Inventors: Chosaku Noda, Hideo Ando