Abstract: Methods and systems for dry etching are disclosed. The system includes a wafer clamp ring having a central opening through which a substrate may be treated and a plurality of smaller, outer support holes for receiving pins from plunger assemblies. The outer support holes are tapered and change in diameter. The tapered shape reduces horizontal shifting of the wafer clamp ring which can occur as the wafer clamp ring is moved up-and-down during operational use. The reduced shifting increases wafer yield along the edges of the wafer.

Abstract: A focus ring for a plasma-based semiconductor processing tool is designed to provide and/or ensure etch rate uniformity across a wafer during a plasma etch process. The focus ring may include an angled inner wall that is angled away from a center of the focus ring to direct a plasma toward the wafer. The angle of the angled inner wall may be greater than approximately 130 degrees relative to the top surface of the wafer and/or may be less than approximately 50 degrees relative to an adjacent lower surface of the focus ring to reduce and/or eliminate areas of overlapping plasma on the wafer (which would otherwise cause non-uniform etch rates). Moreover, an inner diameter may be configured to be in a range of approximately 209 millimeters to 214 millimeters to further reduce and/or eliminate areas of overlapping plasma on the wafer.

Abstract: Methods and systems for uniformly cooling a dome within a plasma treatment system are disclosed. The methods and systems utilize a diffuser including a perforated plate and a cone. The perforated plate includes a center portion and multiple arrays of holes with each array being located circumferentially at a different distance from the center. The cone extends away from the center. The diffuser spreads cooling gas more uniformly across the surface of the dome.

Abstract: A focus ring for a plasma-based semiconductor processing tool is designed to provide and/or ensure etch rate uniformity across a wafer during a plasma etch process. The focus ring may include an angled inner wall that is angled away from a center of the focus ring to direct a plasma toward the wafer. The angle of the angled inner wall may be greater than approximately 130 degrees relative to the top surface of the wafer and/or may be less than approximately 50 degrees relative to an adjacent lower surface of the focus ring to reduce and/or eliminate areas of overlapping plasma on the wafer (which would otherwise cause non-uniform etch rates). Moreover, an inner diameter may be configured to be in a range of approximately 209 millimeters to 214 millimeters to further reduce and/or eliminate areas of overlapping plasma on the wafer.

Abstract: A method of fabricating a dual damascene structure includes etching a via through a first dielectric layer above a substrate, a barrier layer on the first dielectric layer, and a second dielectric layer on the barrier layer. The via is at least partially filled with a photoresist plug. The plug is etched back. A trench is etched through the second dielectric layer. The trench is aligned with the via. The substrate having the first and second dielectric layers thereon is wet with an acid for a sufficient length of time to remove a via fence formed in the trench. The via and the trench are filled with metal.

Abstract: A method of fabricating a dual damascene structure includes etching a via through a first dielectric layer above a substrate, a barrier layer on the first dielectric layer, and a second dielectric layer on the barrier layer. The via is at least partially filled with a photoresist plug. The plug is etched back. A trench is etched through the second dielectric layer. The trench is aligned with the via. The substrate having the first and second dielectric layers thereon is wet with an acid for a sufficient length of time to remove a via fence formed in the trench. The via and the trench are filled with metal.

Abstract: A method for reworking a metal particulate contaminated semiconductor wafer process surface following a metal dry etchback process including providing a semiconductor wafer including a dielectric insulating layer having anisotropically etched openings lined with a first barrier/adhesion layer formed according to a blanket deposition process and an overlying metal layer formed according to a blanket deposition process filling the anisotropically etched openings; dry etching in an etchback process to remove the metal layer to form a process surface revealing at least a portion of the first barrier/adhesion layer; performing a chemical mechanical polishing (CMP) process to rework the process surface to remove a remaining portion of the metal layer including the first barrier/adhesion layer to endpoint detection of the dielectric insulating layer; and, blanket depositing a second barrier/adhesion layer over the dielectric insulating layer.

Abstract: A method for reworking a metal particulate contaminated semiconductor wafer process surface following a metal dry etchback process including providing a semiconductor wafer including a dielectric insulating layer having anisotropically etched openings lined with a first barrier/adhesion layer formed according to a blanket deposition process and an overlying metal layer formed according to a blanket deposition process filling the anisotropically etched openings; dry etching in an etchback process to remove the metal layer to form a process surface revealing at least a portion of the first barrier/adhesion layer; performing a chemical mechanical polishing (CMP) process to rework the process surface to remove a remaining portion of the metal layer including the first barrier/adhesion layer to endpoint detection of the dielectric insulating layer; and, blanket depositing a second barrier/adhesion layer over the dielectric insulating layer.