Patents by Inventor Chou H. Li

Chou H. Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7118942
    Abstract: A method of mass-producing a solid state device comprises providing an atomically smooth, solid state material layer no more than 40 Angstroms thick. This layer is uniformly and defect-freely bonded onto a substrate to provide an acceptable device yield.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: October 10, 2006
    Inventor: Chou H. Li
  • Patent number: 7038290
    Abstract: An integrated circuit device comprising: a body of a first solid material having an upper surface and a major bottom surface; a pocket of a second solid material having a top surface and a side surface, and a bottom surface which contacts a selected portion of said upper surface on said body; said first and second solid materials being so selected as to form, where said pocket contacts said body at said selected portion of said upper surface, an electronic interfacial barrier which is substantially conductive under an applied bias of at least one selected polarity; and a solid electrically insulating region which meets said barrier and adjoins both said body and at least a line on said side surface of said pocket; wherein at least a part of said solid electrically insulating region comprises nitrogen located at least below the level of said electronic interfacial barrier.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: May 2, 2006
    Inventor: Chou H. Li
  • Patent number: 6979877
    Abstract: A method of making dielectrically isolated solid state device comprising state device (including integrated circuits) comprises providing a silicon wafer having a PN junction or other electronic rectifying barrier contained therein and thermally growing or ion-implanting selected ions to an oxide or nitride isolating groove in-situ to isolate it into a plurality of physically integral pockets for use as electrically separately operable components. The groove has a symmetrical, centrally rounded bottom which is located within a few microns below the PN junction or rectifying barrier. Through the unique oxide/nitride forming conditions and through curvature, symmetry, and proximity effects, novel passivation and isolation results obtain.
    Type: Grant
    Filed: September 27, 1994
    Date of Patent: December 27, 2005
    Inventor: Chou H. Li
  • Patent number: 6976904
    Abstract: A liquid suspension for planarizing an outer surface of a material comprises a liquid suspension medium of a specific liquid density; and a plurality of solid, contact-sensitive abrasive particles of a constant solid density and suspended in the liquid suspension medium. The liquid and solid densities are approximately the same so that the abrasive particles freely and stably suspend in the liquid suspension medium, without gravitational separation by settling down or floating up. In this way, damaging contacts of the solid abrasive particles with one another are minimized.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: December 20, 2005
    Assignee: Li Family Holdings, Ltd.
    Inventors: Chou H. Li, Suzanne C. Li
  • Patent number: 6938815
    Abstract: Methods of making improved electronic systems and circuits boards, and more specifically to methods of making improved electronic systems and circuits boards using heat-resistant composite materials having superior mechanical, thermal, and electrical properties.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: September 6, 2005
    Inventor: Chou H. Li
  • Patent number: 6849918
    Abstract: An improved, surface-passivated and electrically isolated solid-state device (including integrated circuits) comprises a silicon wafer with a PN junction or other electronic rectifying barrier contained therein and thermally grown or ion-implanted oxide or nitride isolating grooves in-situ formed in the wafer to isolate it into a plurality of physically integral pockets for use as electrically separately operable components. The grooves have symmetrical, centrally rounded bottoms which are located within a few microns below the PN junction or rectifying barrier. Through the unique oxide/nitride forming conditions and through curvature, symmetry, and proximity effects, novel passivation and isolation results obtain.
    Type: Grant
    Filed: November 15, 1994
    Date of Patent: February 1, 2005
    Inventor: Chou H. Li
  • Patent number: 6784515
    Abstract: A solid state device comprises a solid state material substrate; two adjacent semiconductor pockets on the substrate; and a gate layer less than 10 Angstroms thick. The gate layer has at least an atomically smooth bottom major surface, and is perfectly bonded onto the substrate to bridge a gap between the two semiconductor pockets.
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: August 31, 2004
    Inventor: Chou H Li
  • Publication number: 20040144999
    Abstract: A commercially mass-produced, integrated circuit including:
    Type: Application
    Filed: January 20, 2004
    Publication date: July 29, 2004
    Inventor: Chou H. Li
  • Patent number: 6676492
    Abstract: A planatizing equipment has solid abrasive particles suspended in a liquid suspension. The solid abrasive particles have on their outer surfaces tiny, hard but brittle working edges and points. The liquid suspension medium and the solid abrasive particles have nearly the same density to prevent the brittle working edges and paints from sufficiently contacting and damaging each other. This significantly lengthens the useful life of the solid abrasive particles.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: January 13, 2004
    Inventor: Chou H. Li
  • Patent number: 6625500
    Abstract: A method for computer-generating interaction-specific knowledge base for rapidly improving or optimizing a performance of an object comprises performing, according to computer-designed test matrices, at least several automatic experimental cycles on selected control variables. In at least one of the automatic experimental cycles after the first the computer plans a new test matrix designed to minimize or remove at least one expected two-variable interaction from a main effect of a designated control variable. A machine operating according to the method is also available.
    Type: Grant
    Filed: March 16, 1999
    Date of Patent: September 23, 2003
    Inventor: Chou H. Li
  • Patent number: 6599781
    Abstract: A method of mass-producing a solid state device comprises supplying a solid state material substrate; providing two adjacent semiconductor pockets on the substrate; and forming a gate layer less than 3 to 40 Angstroms thick. The gate layer has atomically smooth major surfaces, and perfectly bonded onto the substrate to bridge a gap between the two semiconductor pockets.
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: July 29, 2003
    Inventor: Chou H. Li
  • Publication number: 20030077995
    Abstract: A liquid suspension for planarizing an outer surface of a material comprises a liquid suspension medium of a specific liquid density; and a plurality of solid, contact-sensitive abrasive particles of a constant solid density and suspended in the liquid suspension medium. The liquid and solid densities are approximately the same so that the abrasive particles freely and stably suspend in the liquid suspension medium, without gravitational separation by settling down or floating up. In this way, damaging contacts of the solid abrasive particles with one another are minimized.
    Type: Application
    Filed: September 30, 2002
    Publication date: April 24, 2003
    Inventors: Chou H. Li, Suzanne C. Li
  • Patent number: 6513024
    Abstract: A method for computer-generating interaction-specific knowledge base for rapidly improving or optimizing a performance of an object comprises performing, according to computer-designed test matrices, at least several automatic experimental cycles on selected control variables. In at least one of the automatic experimental cycles after the first the computer plans a new test matrix designed to minimize or remove at least one expected two-variable interaction from a main effect of a designated control variable. A machine operating according to the method is also available.
    Type: Grant
    Filed: March 16, 1999
    Date of Patent: January 28, 2003
    Inventor: Chou H. Li
  • Publication number: 20020173252
    Abstract: Polishing compositions and tools for achieving polishing
    Type: Application
    Filed: May 16, 2002
    Publication date: November 21, 2002
    Inventor: Chou H. Li
  • Publication number: 20020157247
    Abstract: Methods of making improved electronic systems and circuits boards, and more specifically to methods of making improved electronic systems and circuits boards using heat-resistant composite materials having superior mechanical, thermal, and electrical properties.
    Type: Application
    Filed: June 25, 2001
    Publication date: October 31, 2002
    Inventor: Chou H. Li
  • Patent number: 6458017
    Abstract: A method for planarizing a material surface by providing a suspension of solid abrasive particles in liquid suspension of medium density dm which is within 2 to 15% of the substantially constant solid density ds. The solid abrasive particles are thus generally freely and stably suspended in the suspension liquid n medium. Damage to the grinding and polishing qualities of the solid particles is minimized through reduced contact and collisions of the solid particles on one another.
    Type: Grant
    Filed: September 8, 1999
    Date of Patent: October 1, 2002
    Inventors: Chou H. Li, Suzanne C. Li
  • Patent number: 6413589
    Abstract: A method of coating a ceramic and bonding ceramic onto a substrate for practical uses over 630° C. includes forming a brazed bonding layer at a contact area between the ceramic and the substrate by a fluidic reaction and causing the bonding layer to wet both the ceramic and substrate with a wetting angle of 0-5° to thereby coat and bond the ceramic onto bond the substrate over the entire contact area with a continuous, essentially 100% dense bonding layer. The bonding layer is so free of bonding defects that the resulting bonded product can withstand repeated thermal shocks by quenching in 0° ice water from a temperature in the range of 630-980° C.
    Type: Grant
    Filed: June 8, 1995
    Date of Patent: July 2, 2002
    Inventor: Chou H. Li
  • Patent number: 6384342
    Abstract: A heat resistant system have electronic circuit components fusion bonded onto a circuit board substrate with a heat-resistant composite material. The composite material consists essentially of a solid heat-resistant reinforcement dispersed in a liquid metal matrix of the composite material. The heat-resistant reinforcement differs in density by substantially uniformly and stably distribute in the liquid composite matrix, with substantially no tendency to either sink down or float up therein. This stably uniform distribution enures improved uniformly, reproducibility and heat resistance of the circuit board.
    Type: Grant
    Filed: June 21, 1999
    Date of Patent: May 7, 2002
    Inventor: Chou H. Li
  • Publication number: 20020051848
    Abstract: A method of coating a ceramic onto a substrate, comprising:
    Type: Application
    Filed: June 8, 1995
    Publication date: May 2, 2002
    Inventor: CHOU H. LI
  • Patent number: 6286206
    Abstract: Methods of making improved electronic systems and circuits boards, and more specifically to methods of making improved electronic systems and circuits boards using heat-resistant composite materials having superior mechanical, thermal, and electrical properties.
    Type: Grant
    Filed: April 2, 1998
    Date of Patent: September 11, 2001
    Inventor: Chou H. Li