Patents by Inventor Chou-Huan Yu
Chou-Huan Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240162406Abstract: A display panel including an array substrate, a light-emitting diode chip, a photosensitive material layer and a photosensitive material layer. The array substrate includes a first electrode pad and a second electrode pad adjacent to the first electrode pad. The light-emitting diode chip includes a first electrode and a second electrode at opposite sides of the light-emitting diode chip, and the first electrode is connected with the first electrode pad. The photosensitive material layer is over the array substrate and surrounds the light-emitting diode chip, in which the photosensitive material layer includes an opening exposing the second electrode pad, a sidewall of the opening has a first portion and a second portion, a slope of the first portion is greater than a slope of the second portion. The transparent conductive layer is over the photosensitive material layer and electrically connects the second electrode pad and the second electrode.Type: ApplicationFiled: October 4, 2023Publication date: May 16, 2024Inventors: Chieh-Ming CHEN, Chou-Huan Yu, Bo-ru Jian, Ta-Wen Liao
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Patent number: 8530144Abstract: A method is provided for fabricating source/drain electrodes of a thin film transistor. The method generally provides a substrate having a first gate electrode and a second gate electrode adjacent and electrically connected. The method further provides coating a photoresist layer on the metal layer, and performing an exposure process on the photoresist layer by a photomask. The method further performs a development process on the exposed photoresist layer to form a photoresist pattern layer with different thicknesses on the metal layer, and then etches the metal layer using the photoresist pattern layer as an etch mask, to form a pair of first source/drain electrodes on the first gate electrode and a pair of second source/drain electrodes on the second gate electrode.Type: GrantFiled: March 8, 2012Date of Patent: September 10, 2013Assignee: AU Optronics Corp.Inventors: Zong-Long Jhang, Chia-Ming Chang, Hsiang-Chih Hsiao, Chun-Yi Chiang, Che-Yung Lai, Chou-Huan Yu, Ta-Wen Liao
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Publication number: 20120270397Abstract: A method is provided for fabricating source/drain electrodes of a thin film transistor. The method generally provides a substrate having a first gate electrode and a second gate electrode adjacent and electrically connected. The method further provides coating a photoresist layer on the metal layer, and performing an exposure process on the photoresist layer by a photomask. The method further performs a development process on the exposed photoresist layer to form a photoresist pattern layer with different thicknesses on the metal layer, and then etches the metal layer using the photoresist pattern layer as an etch mask, to form a pair of first source/drain electrodes on the first gate electrode and a pair of second source/drain electrodes on the second gate electrode.Type: ApplicationFiled: March 8, 2012Publication date: October 25, 2012Applicant: AU OPTRONICS CORP.Inventors: Zong-Long Jhang, Chia-Ming Chang, Hsiang-Chih Hsiao, Chun-Yi Chiang, Che-Yung Lai, Chou-Huan Yu, Ta-Wen Liao
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Patent number: 8153337Abstract: A photomask for fabricating a thin film transistor (TFT) is disclosed. The photomask includes a translucent layer disposed on a transparent substrate and covering U-shaped and rectangular channel-forming regions of the transparent substrate. First and second light-shielding layers are disposed on the translucent layer and located at the outer and inner sides of the U-shaped channel-forming region, respectively, and third and fourth light-shielding layers are disposed on the translucent layer and located at opposite sides of the rectangular channel-forming region, respectively, to serve as source/drain-forming regions. An end of the third light-shielding layer extends to the first light-shielding layer. A plurality of first light-shielding islands is disposed on the translucent layer and located within the rectangular channel-forming region. A method for fabricating source/drain electrodes of a TFT is also disclosed.Type: GrantFiled: December 3, 2009Date of Patent: April 10, 2012Assignee: AU Optronics Corp.Inventors: Zong-Long Jhang, Chia-Ming Chang, Hsiang-Chih Hsiao, Chun-Yi Chiang, Che-Yung Lai, Chou-Huan Yu, Ta-Wen Liao
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Patent number: 7989243Abstract: A pixel structure fabricating method is provided. A gate is formed on a substrate. A gate insulation layer covering the gate is formed on the substrate. A channel layer, a source, and a drain are simultaneously formed on the gate insulation layer above the gate. The gate, channel layer, source, and drain form a thin film transistor (TFT). A passivation layer is formed on the TFT and the gate insulation layer. A black matrix is formed on the passivation layer. The black matrix has a contact opening above the drain and a color filter containing opening. A color filer layer is formed within the color filter containing opening through inkjet printing. A dielectric layer is formed on the black matrix and the color filter layer. The dielectric layer and the passivation layer are patterned to expose the drain. A pixel electrode electrically connected to the drain is formed.Type: GrantFiled: March 5, 2009Date of Patent: August 2, 2011Assignee: Au Optronics CorporationInventors: Ta-Wen Liao, Chen-Pang Tung, Chia-Ming Chang, Zong-Long Jhang, Che-Yung Lai, Chun-Yi Chiang, Chou-Huan Yu, Hsiang-Chih Hsiao, Han-Tang Chou, Jun-Kai Chang
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Publication number: 20110053323Abstract: A photomask for fabricating a thin film transistor (TFT) is disclosed. The photomask includes a translucent layer disposed on a transparent substrate and covering U-shaped and rectangular channel-forming regions of the transparent substrate. First and second light-shielding layers are disposed on the translucent layer and located at the outer and inner sides of the U-shaped channel-forming region, respectively, and third and fourth light-shielding layers are disposed on the translucent layer and located at opposite sides of the rectangular channel-forming region, respectively, to serve as source/drain-forming regions. An end of the third light-shielding layer extends to the first light-shielding layer. A plurality of first light-shielding islands is disposed on the translucent layer and located within the rectangular channel-forming region. A method for fabricating source/drain electrodes of a TFT is also disclosed.Type: ApplicationFiled: December 3, 2009Publication date: March 3, 2011Applicant: AU OPTRONICS CORP.Inventors: Zong-Long Jhang, Chia-Ming Chang, Hsiang-Chih Hsiao, Chun-Yi Chiang, Che-Yung Lai, Chou-Huan Yu, Ta-Wen Liao
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Patent number: 7645649Abstract: A pixel structure fabricating method is provided. A gate and a gate insulation layer covering the gate are formed on a substrate. A channel layer is formed on the gate insulation layer. A conductive layer is formed on the channel layer and gate insulation layer. A black matrix having a color filer layer accommodating opening is formed on the conductive layer. The black matrix includes a first block and a second block which is thicker than the first block. The conductive layer is patterned with the black matrix as a mask to form a source and a drain on the channel layer. A color filter layer is formed within the color filter layer accommodating opening through inkjet printing. A dielectric layer is formed on the black matrix and color filter layer. The dielectric layer is patterned to expose the drain. A pixel electrode electrically connected to the drain is formed.Type: GrantFiled: October 1, 2008Date of Patent: January 12, 2010Assignee: Au Optronics CorporationInventors: Che-Yung Lai, Zong-Long Jhang, Chia-Chi Tsai, Chen-Pang Tung, Chia-Ming Chang, Chun-Yi Chiang, Chou-Huan Yu, Hsiang-Chih Hsiao, Han-Tang Chou, Jun-Kai Chang, Ta-Wen Liao
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Publication number: 20100003792Abstract: A pixel structure fabricating method is provided. A gate and a gate insulation layer covering the gate are formed on a substrate. A channel layer is formed on the gate insulation layer. A conductive layer is formed on the channel layer and gate insulation layer. A black matrix having a color filer layer accommodating opening is formed on the conductive layer. The black matrix includes a first block and a second block which is thicker than the first block. The conductive layer is patterned with the black matrix as a mask to form a source and a drain on the channel layer. A color filter layer is formed within the color filter layer accommodating opening through inkjet printing. A dielectric layer is formed on the black matrix and color filter layer. The dielectric layer is patterned to expose the drain. A pixel electrode electrically connected to the drain is formed.Type: ApplicationFiled: October 1, 2008Publication date: January 7, 2010Applicant: AU OPTRONICS CORPORATIONInventors: Che-Yung Lai, Zong-Long Jhang, Chia-Chi Tsai, Chen-Pang Tung, Chia-Ming Chang, Chun-Yi Chiang, Chou-Huan Yu, Hsiang-Chih Hsiao, Han-Tang Chou, Jun-Kai Chang, Ta-Wen Liao
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Publication number: 20100003774Abstract: A pixel structure fabricating method is provided. A gate is formed on a substrate. A gate insulation layer covering the gate is formed on the substrate. A channel layer, a source, and a drain are simultaneously formed on the gate insulation layer above the gate. The gate, channel layer, source, and drain form a thin film transistor (TFT). A passivation layer is formed on the TFT and the gate insulation layer. A black matrix is formed on the passivation layer. The black matrix has a contact opening above the drain and a color filter containing opening. A color filer layer is formed within the color filter containing opening through inkjet printing. A dielectric layer is formed on the black matrix and the color filter layer. The dielectric layer and the passivation layer are patterned to expose the drain. A pixel electrode electrically connected to the drain is formed.Type: ApplicationFiled: March 5, 2009Publication date: January 7, 2010Applicant: AU OPTRONICS CORPORATIONInventors: Ta-Wen Liao, Chen-Pang Tung, Chia-Ming Chang, Zong-Long Jhang, Che-Yung Lai, Chun-Yi Chiang, Chou-Huan Yu, Hsiang-Chih Hsiao, Han-Tang Chou, Jun-Kai Chang
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Patent number: 7598102Abstract: A fabricating method for a pixel structure including following procedures is provided. First, a gate and a gate insulator layer are formed sequentially on a substrate. Next, a semiconductor layer, a conductive layer and a photosensitive black matrix having a color filter containing opening are sequentially formed on the gate insulator layer. The photosensitive black matrix includes a first portion and a second portion. A thickness of the first portion is smaller than that of the second portion. A channel, a source and a drain are formed simultaneously using the photosensitive black matrix as a mask. A passivation is formed on the substrate, and a color filer layer is formed within the color filter containing opening via an inkjet printing process and a dielectric layer is formed thereon. Next, a patterning process is applied to expose the drain. Ultimately, a pixel electrode connected to the drain is formed.Type: GrantFiled: July 31, 2008Date of Patent: October 6, 2009Assignee: Au Optronics CorporationInventors: Chou-Huan Yu, Chun-Yi Chiang, Chia-Chi Tsai, Chen-Pang Tung, Hsiang-Chih Hsiao, Chia-Ming Chang, Zong-Long Jhang, Che-Yung Lai, Han-Tang Chou, Jun-Kai Chang, Ta-Wen Liao