Patents by Inventor Chou-Kun LIN
Chou-Kun LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10643986Abstract: A device comprises a first interconnect structure over a first active device layer, a first power circuit in the first active device layer, a second active device layer over and in contact with the first interconnect structure, a first switch in the second active device layer, a second interconnect structure over and in contact with the second active device layer, a third active device layer over and in contact with the second interconnect structure, a second power circuit in the third active device layer and a third interconnect structure over and in contact with the third active device layer and connected to a power source, wherein the power source is configured to provide power to the first power circuit through the first switch.Type: GrantFiled: September 10, 2018Date of Patent: May 5, 2020Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang, Kuo-Nan Yang, Chung-Hsing Wang
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Publication number: 20190006346Abstract: A device comprises a first interconnect structure over a first active device layer, a first power circuit in the first active device layer, a second active device layer over and in contact with the first interconnect structure, a first switch in the second active device layer, a second interconnect structure over and in contact with the second active device layer, a third active device layer over and in contact with the second interconnect structure, a second power circuit in the third active device layer and a third interconnect structure over and in contact with the third active device layer and connected to a power source, wherein the power source is configured to provide power to the first power circuit through the first switch.Type: ApplicationFiled: September 10, 2018Publication date: January 3, 2019Inventors: Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang, Kuo-Nan Yang, Chung-Hsing Wang
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Patent number: 10074641Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.Type: GrantFiled: October 23, 2017Date of Patent: September 11, 2018Assignee: Taiwan Semicondcutor Manufacturing CompanyInventors: Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang, Kuo-Nan Yang, Chung-Hsing Wang
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Patent number: 9984192Abstract: An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist.Type: GrantFiled: February 15, 2016Date of Patent: May 29, 2018Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Kuo-Nan Yang, Chou-Kun Lin, Jerry Chang-Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang
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Publication number: 20180047716Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.Type: ApplicationFiled: October 23, 2017Publication date: February 15, 2018Inventors: Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang, Kuo-Nan Yang, Chung-Hsing Wang
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Patent number: 9799639Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.Type: GrantFiled: March 15, 2016Date of Patent: October 24, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang, Kuo-Nan Yang, Chung-Hsing Wang
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Patent number: 9666490Abstract: Methods for fabricating multiple inverter structures in a multi-layer semiconductor structure are provided. A first device layer is formed on a substrate. The first device layer comprises one or more first inverter structures including a first input terminal and a first output terminal. A second device layer is formed on the first device layer. The second device layer comprises one or more second inverter structures including a second input terminal and a second output terminal. One or more inter-layer connection structures are formed. The one or more inter-layer connection structures are disposed to electrically connect the first input terminal to the second output terminal and electrically connect the first output terminal to the second input terminal.Type: GrantFiled: June 6, 2016Date of Patent: May 30, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: I-Fan Lin, Yi-Tang Lin, Cheng-Hung Yeh, Hsien-Hsin Sean Lee, Chou-Kun Lin
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Patent number: 9509301Abstract: A circuit is disclosed that includes a plurality of voltage control circuits. Each voltage control circuit of the voltage control circuits includes a driver circuit and a switch circuit. The driver circuit is configured to receive a control signal having a series of pulses. The switch circuit is configured to generate a driving voltage when being turned on. The driver circuit alternately turns on and off the switch circuit in accordance with the series of pulses.Type: GrantFiled: June 28, 2013Date of Patent: November 29, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jerry Chang-Jui Kao, Chien-Ju Chao, Chou-Kun Lin, Chin-Shen Lin, King-Ho Tam, Kuo-Nan Yang, Chung-Hsing Wang
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Patent number: 9501602Abstract: In some embodiments, in a method, placement of a design layout is performed. The design layout includes a power rail segment, several upper-level power lines and several cells. The upper-level power lines cross over and bound the power rail segment at where the upper-level power lines intersect with the power rail segment. The cells are powered through the power rail segment. For each cell, a respective current through the power rail segment during a respective SW of the cell is obtained. One or more groups of cells with overlapped SWs are determined. One or more EM usages of the power rail segment by the one or more groups of cells using the respective currents of each group of cells are obtained. The design layout is adjusted when any of the one or more EM usages of the power rail segment causes an EM susceptibility of the power rail segment.Type: GrantFiled: April 17, 2014Date of Patent: November 22, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Nitesh Katta, Jerry Chang-Jui Kao, Chin-Shen Lin, Yi-Chuin Tsai, Chou-Kun Lin, Kuo-Nan Yang, Chung-Hsing Wang
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Publication number: 20160284603Abstract: Systems and methods are provided for fabricating a semiconductor structure including an inverter chain. An example semiconductor structure includes a first device layer, a second device layer, and one or more inter-layer connection structures. The first device layer is formed on a substrate and includes one or more first inverter structures. The second device layer is formed on the first device layer and includes one or more second inverter structures. The one or more inter-layer connection structures are configured to electrically connect to the first inverter structures and the second inverter structures.Type: ApplicationFiled: June 6, 2016Publication date: September 29, 2016Inventors: I-Fan Lin, YI-TANG LIN, CHENG-HUNG YEH, HSIEN-HSIN SEAN LEE, CHOU-KUN LIN
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Patent number: 9405883Abstract: A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a part of a power rail in at least one design file of a semiconductor device and is enclosed by only two terminal via arrays. A second criteria is determined to be met when a length of the metal segment is not larger than a electromigration critical length. The metal segment is included in the semiconductor device with a first current density limit depending on the length of the metal segment when the first and the second criteria are met.Type: GrantFiled: September 17, 2015Date of Patent: August 2, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Shen Lin, Jerry Chang-Jui Kao, Nitesh Katta, Chou-Kun Lin, Yi-Chuin Tsai, Chi-Yeh Yu, Kuo-Nan Yang
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Publication number: 20160197068Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.Type: ApplicationFiled: March 15, 2016Publication date: July 7, 2016Inventors: Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang, Kuo-Nan Yang, Chung-Hsing Wang
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Patent number: 9373623Abstract: Systems and methods are provided for fabricating a semiconductor structure including an inverter chain. An example semiconductor structure includes a first device layer, a second device layer, and one or more inter-layer connection structures. The first device layer is formed on a substrate and includes one or more first inverter structures. The second device layer is formed on the first device layer and includes one or more second inverter structures. The one or more inter-layer connection structures are configured to electrically connect to the first inverter structures and the second inverter structures.Type: GrantFiled: December 20, 2013Date of Patent: June 21, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: I-Fan Lin, Yi-Tang Lin, Cheng-Hung Yeh, Hsien-Hsin Sean Lee, Chou-Kun Lin
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Publication number: 20160162619Abstract: An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist.Type: ApplicationFiled: February 15, 2016Publication date: June 9, 2016Inventors: Kuo-Nan Yang, Chou-Kun Lin, Jerry Chang-Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang
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Patent number: 9287257Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.Type: GrantFiled: August 27, 2014Date of Patent: March 15, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang, Kuo-Nan Yang, Chung-Hsing Wang
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Patent number: 9262573Abstract: An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist.Type: GrantFiled: March 8, 2013Date of Patent: February 16, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Nan Yang, Chou-Kun Lin, Jerry Chang-Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang
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Publication number: 20160004809Abstract: A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a part of a power rail in at least one design file of a semiconductor device and is enclosed by only two terminal via arrays. A second criteria is determined to be met when a length of the metal segment is not larger than a electromigration critical length. The metal segment is included in the semiconductor device with a first current density limit depending on the length of the metal segment when the first and the second criteria are met.Type: ApplicationFiled: September 17, 2015Publication date: January 7, 2016Inventors: Chin-Shen LIN, Jerry Chang-Jui KAO, Nitesh KATTA, Chou-Kun LIN, Yi-Chuin TSAI, Chi-Yeh YU, Kuo-Nan YANG
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Publication number: 20150348962Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.Type: ApplicationFiled: August 27, 2014Publication date: December 3, 2015Inventors: Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang, Kuo-Nan Yang, Chung-Hsing Wang
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Patent number: 9171926Abstract: An integrated circuit includes a first and a second standard cell. The first standard cell includes a first gate electrode, and a first channel region underlying the first gate electrode. The first channel region has a first channel doping concentration. The second standard cell includes a second gate electrode, and a second channel region underlying the second gate electrode. The second channel region has a second channel doping concentration. A dummy gate includes a first half and a second half in the first and the second standard cells, respectively. The first half and the second half are at the edges of the first and the second standard cells, respectively, and are abutted to each other. A dummy channel is overlapped by the dummy gate. The dummy channel has a third channel doping concentration substantially equal to a sum of the first channel doping concentration and the second channel doping concentration.Type: GrantFiled: November 18, 2014Date of Patent: October 27, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Nan Yang, Chou-Kun Lin, Jerry Chang-Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang
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Publication number: 20150302128Abstract: In some embodiments, in a method, placement of a design layout is performed. The design layout includes a power rail segment, several upper-level power lines and several cells. The upper-level power lines cross over and bound the power rail segment at where the upper-level power lines intersect with the power rail segment. The cells are powered through the power rail segment. For each cell, a respective current through the power rail segment during a respective SW of the cell is obtained. One or more groups of cells with overlapped SWs are determined. One or more EM usages of the power rail segment by the one or more groups of cells using the respective currents of each group of cells are obtained. The design layout is adjusted when any of the one or more EM usages of the power rail segment causes an EM susceptibility of the power rail segment.Type: ApplicationFiled: April 17, 2014Publication date: October 22, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: NITESH KATTA, JERRY CHANG-JUI KAO, CHIN-SHEN LIN, YI-CHUIN TSAI, CHOU-KUN LIN, KUO-NAN YANG, CHUNG-HSING WANG